ETRA SOM/ETRA Hardware/Peripherals/Watchdog
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| Version | Issue Date | Notes | |
| 0.9.0 | Dec 2020 | First Draft | |
| [TBD_link X.Y.Z] | Month Year | TBD | |
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Contents
Peripheral Watchdog[edit | edit source]
Description[edit | edit source]
The Watchdog interfaces available on ETRA SoM are based on STM32MP1 SoC.
The Watchdog portssupports the following standards and features:
- Two independent watchdogs (IWDG1 and IWDG2) dedicated to MPU
- 12-bit down-counter and 8-bit prescaler
- Dual voltage domain, thus enabling operation in low-power modes
- Independent 32 kHz internal RC clock that operate in Stop and Standby modes
- One window watchdog (WWDG1) dedicated to the MCU
- Programmable free-running 7-bit downcounter
- Conditional reset
- Early wakeup interrupt
- can be frozen in debug mode
- The MPU can receive an interrupt if the WWDG1 generates a reset
