Difference between revisions of "ETRA SOM/ETRA Hardware/Peripherals/Watchdog"
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! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History | ! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History | ||
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=== Description === | === Description === | ||
| − | The Watchdog interfaces available on ETRA | + | The Watchdog interfaces available on ETRA SOM are based on STM32MP1 SoC. |
The Watchdog portssupports the following standards and features: | The Watchdog portssupports the following standards and features: | ||
| − | * | + | * two independent watchdogs (IWDG1 and IWDG2) dedicated to MPU |
** 12-bit down-counter and 8-bit prescaler | ** 12-bit down-counter and 8-bit prescaler | ||
| − | ** | + | ** dual voltage domain, thus enabling operation in low-power modes |
| − | ** | + | ** independent 32 kHz internal RC clock that operate in Stop and Standby modes |
| − | * | + | * one window watchdog (WWDG1) dedicated to the MCU |
| − | ** | + | ** programmable free-running 7-bit downcounter |
| − | ** | + | ** conditional reset |
| − | ** | + | ** early wakeup interrupt |
| − | **can be frozen in debug mode | + | ** can be frozen in debug mode |
| − | * | + | * the MPU can receive an interrupt if the WWDG1 generates a reset |
---- | ---- | ||
[[Category:ETRA]] | [[Category:ETRA]] | ||
Latest revision as of 11:45, 8 January 2024
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| History | |||
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| Issue Date | Notes | ||
| 2020/12/31 | First Release | ||
Contents
Peripheral Watchdog[edit | edit source]
Description[edit | edit source]
The Watchdog interfaces available on ETRA SOM are based on STM32MP1 SoC.
The Watchdog portssupports the following standards and features:
- two independent watchdogs (IWDG1 and IWDG2) dedicated to MPU
- 12-bit down-counter and 8-bit prescaler
- dual voltage domain, thus enabling operation in low-power modes
- independent 32 kHz internal RC clock that operate in Stop and Standby modes
- one window watchdog (WWDG1) dedicated to the MCU
- programmable free-running 7-bit downcounter
- conditional reset
- early wakeup interrupt
- can be frozen in debug mode
- the MPU can receive an interrupt if the WWDG1 generates a reset
