Difference between revisions of "ETRA SOM/ETRA Hardware/Peripherals/Watchdog"

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__FORCETOC__
 
__FORCETOC__
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<section begin="Body" />
  
 
==Peripheral Watchdog ==
 
==Peripheral Watchdog ==
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''TBD: sostituire le sezioni con le informazioni sull'uso della periferica''
 
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''Nell'esempio di seguito c'è la descrizione dell'interfaccia HDMI''
 
  
 
=== Description  ===
 
=== Description  ===
  
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The Watchdog interface available on ETRA is based on xxxxx ''TBD:SOC name'' SoC.  
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The Watchdog interfaces available on ETRA SOM are based on STM32MP1 SoC.  
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The Watchdog port supports the following standards and features:
 
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* High-Definition Multimedia Interface Specification, Version 1.4a
 
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* Support for up to 1080p at 60Hz HDTV display resolutions and up to QXGA graphic display resolutions.
 
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* Support for 4k x 2k and 3D video formats
 
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* Support for up to 16-bit Deep Color modes
 
  
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===Pin mapping===
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The Watchdog portssupports the following standards and features:
  
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The Pin mapping is described in the [[ETRA SOM/ETRA Hardware/Pinout_Table | Pinout table section]]
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* two independent watchdogs (IWDG1 and IWDG2) dedicated to MPU
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** 12-bit down-counter and 8-bit prescaler
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** dual voltage domain, thus enabling operation in low-power modes
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** independent 32 kHz internal RC clock that operate in Stop and Standby modes
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* one window watchdog (WWDG1) dedicated to the MCU
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** programmable free-running 7-bit downcounter
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** conditional reset
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** early wakeup interrupt
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** can be frozen in debug mode
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* the MPU can receive an interrupt if the WWDG1 generates a reset
  
 
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[[Category:ETRA]]
 
[[Category:ETRA]]

Latest revision as of 11:45, 8 January 2024

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History
Issue Date Notes
2020/12/31 First Release



Peripheral Watchdog[edit | edit source]

Description[edit | edit source]

The Watchdog interfaces available on ETRA SOM are based on STM32MP1 SoC.

The Watchdog portssupports the following standards and features:

  • two independent watchdogs (IWDG1 and IWDG2) dedicated to MPU
    • 12-bit down-counter and 8-bit prescaler
    • dual voltage domain, thus enabling operation in low-power modes
    • independent 32 kHz internal RC clock that operate in Stop and Standby modes
  • one window watchdog (WWDG1) dedicated to the MCU
    • programmable free-running 7-bit downcounter
    • conditional reset
    • early wakeup interrupt
    • can be frozen in debug mode
  • the MPU can receive an interrupt if the WWDG1 generates a reset
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