Difference between revisions of "ETRA SOM/ETRA Hardware/Peripherals/SPI"
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| − | !style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date | + | ! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date |
| − | !style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes | + | ! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes |
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| − | |style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"| | + | | style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |0.9.0 |
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| − | |style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"| | + | | style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First Draft |
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| − | |style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Month Year | + | | style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Month Year |
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| − | <section end=History/> | + | <section end="History" /> |
__FORCETOC__ | __FORCETOC__ | ||
| − | <section begin=Body/> | + | <section begin="Body" /> |
==Peripheral SPI == | ==Peripheral SPI == | ||
| − | + | The Serial Peripheral Interface (SPI) is a full-duplex, synchronous, four-wire serial communication block. | |
| − | |||
=== Description === | === Description === | ||
| − | The SPI interface available on ETRA is based on | + | The SPI interface available on ETRA SoM is based on STM32MP1 SoC. |
The SPI port supports the following standards and features: | The SPI port supports the following standards and features: | ||
| − | * | + | * full-duplex synchronous transfers on three lines |
| − | * | + | * half-duplex synchronous transfer on two lines (with bidirectional data line) |
| − | * | + | * simplex synchronous transfers on two lines (with unidirectional data line) |
| − | * | + | * 4-bit to 32-bit data size selection |
| + | * multi master or multi slave mode capability | ||
| + | * hardware or software management of SS for both master and slave | ||
| + | * configurable SS signal polarity and timing, MISO x MOSI swap capability | ||
| + | * two 16x or 8x 8-bit embedded Rx and TxFIFOs with DMA capability | ||
===Pin mapping=== | ===Pin mapping=== | ||
Revision as of 11:01, 30 December 2020
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| History | |||
|---|---|---|---|
| Version | Issue Date | Notes | |
| 0.9.0 | Dec 2020 | First Draft | |
| [TBD_link X.Y.Z] | Month Year | TBD | |
| ... | ... | ... | |
Peripheral SPI[edit | edit source]
The Serial Peripheral Interface (SPI) is a full-duplex, synchronous, four-wire serial communication block.
Description[edit | edit source]
The SPI interface available on ETRA SoM is based on STM32MP1 SoC.
The SPI port supports the following standards and features:
- full-duplex synchronous transfers on three lines
- half-duplex synchronous transfer on two lines (with bidirectional data line)
- simplex synchronous transfers on two lines (with unidirectional data line)
- 4-bit to 32-bit data size selection
- multi master or multi slave mode capability
- hardware or software management of SS for both master and slave
- configurable SS signal polarity and timing, MISO x MOSI swap capability
- two 16x or 8x 8-bit embedded Rx and TxFIFOs with DMA capability
Pin mapping[edit | edit source]
The Pin mapping is described in the Pinout table section
