Difference between revisions of "BORA Xpress SOM/BORA Xpress Hardware/Peripherals/Static memory controller"
(Created page with "{{#lst:Processing_system_peripherals_(BORAXpress)|NAND}}") |
|||
| Line 1: | Line 1: | ||
| + | <section begin=History/> | ||
| + | {| style="border-collapse:collapse; " | ||
| + | !colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History | ||
| + | |- | ||
| + | !style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date | ||
| + | !style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes | ||
| + | |- | ||
| + | |style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|2021/11/22 | ||
| + | |style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|New documentation layout | ||
| + | |- | ||
| + | |} | ||
| + | <section end=History/> | ||
| + | __FORCETOC__ | ||
| + | <section begin=Body/> | ||
{{#lst:Processing_system_peripherals_(BORAXpress)|NAND}} | {{#lst:Processing_system_peripherals_(BORAXpress)|NAND}} | ||
| + | <section end=Body/> | ||
| + | |||
| + | [[Category:BORA Xpress]] | ||
Latest revision as of 15:15, 11 January 2024
| HOME | SOMs | SBCs | ToloMEO Embedded Assistant |  GET A QUOTE
|
 ONLINE HELPDESK
|
| Roadmap | IoT Services | ML/AI services | Embedded Design Services |
| History | |||
|---|---|---|---|
| Issue Date | Notes | ||
| 2021/11/22 | New documentation layout | ||
Static memory controller (SMC) signals are routed to the connectors to connect an external flash NAND memory chip. The following table describes the interface signals:
| Pin name | Conn. pin | Function | Notes |
|---|---|---|---|
| NAND_CS0 | J1.122 | NAND flash chip select | MIO bank 0, pin 0 |
| NAND_IO0 | J1.119 | NAND I/O 0 | MIO bank 0, pin 5 |
| NAND_IO1 | J1.129 | NAND I/O 1 | MIO bank 0, pin 6 |
| NAND_IO2 | J1.121 | NAND I/O 2 | MIO bank 0, pin 4 |
| NAND_IO3 | J1.124 | NAND I/O 3 | MIO bank 0, pin 13 |
| NAND_IO4 | J1.126 | NAND I/O 4 | MIO bank 0, pin 9 |
| NAND_IO5 | J1.128 | NAND I/O 5 | MIO bank 0, pin 10 |
| NAND_IO6 | J1.132 | NAND I/O 6 | MIO bank 0, pin 11 |
| NAND_IO7 | J1.134 | NAND I/O 7 | MIO bank 0, pin 12 |
| NAND_WE | J1.123 | NAND write enable | MIO bank 0, pin 3 |
| NAND_ALE | J1.125 | NAND address latch | MIO bank 0, pin 2 |
| NAND_BUSY | J1.131 | NAND Busy | MIO bank 0, pin 14 |
| NAND_RE | J1.136 | NAND read enable | MIO bank 0, pin 8 |
| NAND_CLE | J1.138 | NAND command latch enable | MIO bank 0, pin 7 |
