Difference between revisions of "BORA SOM/BORA Hardware/Peripherals/Processing System (PS)"
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| + | <section begin=History/> | ||
| + | {| style="border-collapse:collapse; " | ||
| + | !colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History | ||
| + | |- | ||
| + | !style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date | ||
| + | !style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes | ||
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| + | |style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|{{oldid|15111|2021/10/29}} | ||
| + | |style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|New documentation layout | ||
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| + | !style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000"|2022/03/01 | ||
| + | !style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000"|Updated MIO pins | ||
| + | |- | ||
| + | |} | ||
| + | <section end=History/> | ||
| + | |||
{{#lst:Processing_system_peripherals_(Bora)|PS}} | {{#lst:Processing_system_peripherals_(Bora)|PS}} | ||
Latest revision as of 13:33, 8 January 2024
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| History | |||
|---|---|---|---|
| Issue Date | Notes | ||
| New documentation layout | |||
| 2022/03/01 | Updated MIO pins | ||
The 54 pins of the MIO module are assigned as reported in the following table:
| MIO Pins | Function |
|---|---|
| MIO[0:14] | Quad-SPI and NAND flash |
| MIO[15] | EX_WDT_REARM (watchdog WDI) Optionally, it can act as SWDT reset out |
| MIO[16:27] | Gigabit Ethernet |
| MIO[28:39] | USB On-The-Go |
| MIO[40:45] | SD/SDIO/MMC |
| MIO[46:47] | I²C0 |
| MIO[48:49] | UART1 |
| MIO[50] | USB PHY reset |
| MIO[51] | ETH0 PHY reset |
| MIO[52] | Ethernet Management Data Clock input |
| MIO[53] | Ethernet Management Data Input/Output |
