BORA SOM/BORA Evaluation Kit/Interfaces and Connectors/JTAG
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JTAG[edit | edit source]
JTAG[edit | edit source]
JTAG port is available as two different mechanical connectors:
- 2.00mm-pitch 7x2 header (Xilinx standard)
- 2.54mm-pitch 10x2 header (ARM standard): http://www2.lauterbach.com/pdf/arm_app_jtag.pdf
- This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations, depending on bootstrap signals. In case split mode is selected, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual.
JTAG XILINX - J13[edit | edit source]
J13 is a 14-pin 7x2x2 pitch vertical header. The following table reports the pinout of the connector:
| Pin# | Pin name | Function | Notes |
|---|---|---|---|
| 1, 3, 5, 7, 9, 11, 13 | DGND | - | - |
| 2 | 3.3V | - | - |
| 4 | JTAG_TMS | - | - |
| 6 | JTAG_TCK | - | - |
| 8 | JTAG_TDO | - | - |
| 10 | JTAG_TDI | - | - |
| 12 | N.C. | - | - |
| 14 | JTAG_TRSTn | - | - |
JTAG ARM - J18[edit | edit source]
J18 is a 20-pin 10x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
| Pin# | Pin name | Function | Notes |
|---|---|---|---|
| 1 | 3.3V | - | - |
| 2 | 3.3V | - | - |
| 3, 11, 17, 19 | N.C. | - | - |
| 4, 6 ,8 ,10 ,12, 14, 16, 18, 20 |
DGND | - | - |
| 5 | JTAG_TDI | - | - |
| 7 | JTAG_TMS | - | - |
| 9 | JTAG_TCK | - | - |
| 13 | JTAG_TDO | - | - |
| 15 | JTAG_TRSTn | - | - |
TRACE[edit | edit source]
Trace Port - J22[edit | edit source]
J22 is a QSH–060–01–L–D–A 0,50 mm Hi-speed socket. It is connected to the Debug Trace Port. From the physical standpoint, trace port exploits the advanced routing of bank 13 signals implemented on Bora, combined with the possibility to select the I/O voltage of bank itself. Connector is compatible with ETMv1/ETMv3 specification. Please refer to http://www.lauterbach.com/frames.html?adetmmipi60.html for more details.
Please note that:
- JTAG and trace signals are EMIO routed to I/O of bank 13
- About tracing, several differents schemes are possible, depending of debug requirements. For example one might be interested in CPU-only tracing via PTM or fabric-only tracing via FTM. For more details please refer to Zynq TRM and these links:
The following table reports the pinout of the connector:
| Pin# | Pin name | Function | Notes |
|---|---|---|---|
| 1 | 3.3V | - | - |
| 2 | JTAG_TMS | - | - |
| 3 | JTAG_TCK | - | - |
| 4 | JTAG_TDO | - | - |
| 5 | JTAG_TDI | - | - |
| 6 | JTAG_TRSTn | - | - |
| 7, 8, 9, 10, 11, 18, 20, 22, 24 ,26, 28, 30, 32, 34, 36, 38, 40 |
N.C. | - | - |
| 12 | VDDIO_BANK13 | - | - |
| 13 | IO_L15N_T2_DQS_13 | - | - |
| 14, 15, 16, ,42, 44, 46, 48, 50, 52, 54, 56, 57, 58, 59, 60 |
DGND | - | - |
| 17 | IO_L15P_T2_DQS_13 | - | - |
| 19 | IO_L17N_T2_13 | - | - |
| 21 | IO_L17P_T2_13 | - | - |
| 23 | IO_L20N_T3_13 | - | - |
| 25 | IO_L20P_T3_13 | - | - |
| 27 | IO_L22N_T3_13 | - | - |
| 29 | IO_L22P_T3_13 | - | - |
| 31 | IO_L6N_T0_VREF_13 | - | - |
| 33 | IO_L12N_T1_MRCC_13 | - | - |
| 35 | IO_L12P_T1_MRCC_13 | - | - |
| 37 | IO_L14N_T2_SRCC_13 | - | - |
| 39 | IO_L14P_T2_SRCC_13 | - | - |
| 41 | IO_L16N_T2_13 | - | - |
| 43 | IO_L16P_T2_13 | - | - |
| 45 | IO_L18N_T2_13 | - | - |
| 47 | IO_L18P_T2_13 | - | - |
| 49 | IO_L19N_T3_VREF_13 | - | - |
| 51 | IO_L19P_T3_13 | - | - |
| 53 | IO_L21N_T3_DQS_13 | - | - |
| 55 | IO_L21P_T3_DQS_13 | - | - |
| 61, 62, 63, 64 | DGND | - | - |
