BORA SOM/BORA Evaluation Kit/Interfaces and Connectors/JTAG
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Revision as of 11:03, 28 October 2021 by U0007 (talk | contribs) (Created page with "<section begin=Body/> {{#lst:BoraEVB|JTAG}} <section end=Body/>")
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JTAG[edit | edit source]
JTAG port is available as two different mechanical connectors:
- 2.00mm-pitch 7x2 header (Xilinx standard)
- 2.54mm-pitch 10x2 header (ARM standard): http://www2.lauterbach.com/pdf/arm_app_jtag.pdf
- This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations, depending on bootstrap signals. In case split mode is selected, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual.
JTAG XILINX - J13[edit | edit source]
J13 is a 14-pin 7x2x2 pitch vertical header. The following table reports the pinout of the connector:
| Pin# | Pin name | Function | Notes |
|---|---|---|---|
| 1, 3, 5, 7, 9, 11, 13 | DGND | - | - |
| 2 | 3.3V | - | - |
| 4 | JTAG_TMS | - | - |
| 6 | JTAG_TCK | - | - |
| 8 | JTAG_TDO | - | - |
| 10 | JTAG_TDI | - | - |
| 12 | N.C. | - | - |
| 14 | JTAG_TRSTn | - | - |
JTAG ARM - J18[edit | edit source]
J18 is a 20-pin 10x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
| Pin# | Pin name | Function | Notes |
|---|---|---|---|
| 1 | 3.3V | - | - |
| 2 | 3.3V | - | - |
| 3, 11, 17, 19 | N.C. | - | - |
| 4, 6 ,8 ,10 ,12, 14, 16, 18, 20 |
DGND | - | - |
| 5 | JTAG_TDI | - | - |
| 7 | JTAG_TMS | - | - |
| 9 | JTAG_TCK | - | - |
| 13 | JTAG_TDO | - | - |
| 15 | JTAG_TRSTn | - | - |
