Difference between revisions of "BORA Lite SOM/Part number composition"

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! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
 
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
 
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |{{oldid|11600|11600}}
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" | Dec 2020
 
 
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" | First version
 
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" | First version
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" | Added SOCs versions
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" | Added explanation NOR SPI size limitation
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" | Added XC7020 speed grade 3
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! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" | Added XC7014S speed grade 1
 
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__FORCETOC__
 
__FORCETOC__
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<section begin="Body" />
  
 
==Part number composition==
 
==Part number composition==
 
BORA Lite SOM module part number is identified by the following digit-code table:
 
BORA Lite SOM module part number is identified by the following digit-code table:
{|class="wikitable" style="width:50%"
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{| class="wikitable" style="width:50%"
!style="width:10%"|Part number structure
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! style="width:10%" |Part number structure
!style="width:40%"|Options
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! style="width:40%" |Options
!style="width:20%"|Description
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! style="width:20%" |Description
 +
|-
 +
!Family
 +
|'''DBT'''
 +
|Family prefix code
 
|-
 
|-
 
!SOC
 
!SOC
 
|
 
|
 +
* A: XC7Z010 ARM Cortex-A9 667MHz - Speed grade ''-1''
 
* D: XC7Z020 ARM Cortex-A9 667MHz - Speed grade ''-1''
 
* D: XC7Z020 ARM Cortex-A9 667MHz - Speed grade ''-1''
 +
* L: XC7Z020 ARM Cortex-A9 667MHz - Speed grade ''-1'' Automotive Grade
 
* J: XC7Z007S ARM Cortex-A9 667MHz - Speed grade ''-1''
 
* J: XC7Z007S ARM Cortex-A9 667MHz - Speed grade ''-1''
 +
* F: XC7Z020 ARM Cortex-A9 866MHz - Speed grade ''-3''
 +
* K: XC7Z014S ARM Cortex-A9 667MHz - Speed grade ''-1''
 
|System on chip definition (and FPGA speed grade)
 
|System on chip definition (and FPGA speed grade)
 
|-
 
|-
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* 0: 0MB
 
* 0: 0MB
 
* 4: 16MB
 
* 4: 16MB
|QUAD SPI NOR flash memory size
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|QUAD SPI NOR flash memory size - The limitation to max 16MB is due to this [https://support.xilinx.com/s/article/57744?language=en_US Errata from Xilinx]. The proposed solution by Xilinx has not been approved by DAVE Embedded Systems
 
|-
 
|-
 
!RAM
 
!RAM

Latest revision as of 12:47, 7 April 2024

History
Issue Date Notes

11600

First version

17185

Added SOCs versions

19369

Added explanation NOR SPI size limitation

20242

Added XC7020 speed grade 3

20317

Added XC7014S speed grade 1



Part number composition[edit | edit source]

BORA Lite SOM module part number is identified by the following digit-code table:

Part number structure Options Description
Family DBT Family prefix code
SOC
  • A: XC7Z010 ARM Cortex-A9 667MHz - Speed grade -1
  • D: XC7Z020 ARM Cortex-A9 667MHz - Speed grade -1
  • L: XC7Z020 ARM Cortex-A9 667MHz - Speed grade -1 Automotive Grade
  • J: XC7Z007S ARM Cortex-A9 667MHz - Speed grade -1
  • F: XC7Z020 ARM Cortex-A9 866MHz - Speed grade -3
  • K: XC7Z014S ARM Cortex-A9 667MHz - Speed grade -1
System on chip definition (and FPGA speed grade)
NOR SPI
  • 0: 0MB
  • 4: 16MB
QUAD SPI NOR flash memory size - The limitation to max 16MB is due to this Errata from Xilinx. The proposed solution by Xilinx has not been approved by DAVE Embedded Systems
RAM
  • 1: 1GB
  • 9: 512MB
DDR3 Memory RAM size
NAND
  • 0: 0MB
  • 1: 1GB NAND SLC
  • 7: 128MB NAND SLC
  • 8: 256MB NAND SLC
  • 9: 512MB NAND SLC
Flash memory NAND size
Boot/Misc
  • 1: NOR boot
Boot options
Temperature range
  • C - Commercial grade: 0 to70°C
  • I - Industrial grade: -40 to 85°C
For the DAVE Embedded Systems' product Temperature Range classification, please find more information at the page Products Classification
PCB revision
  • 0: first version
PCB release may change for manufacturing purposes (i.e. text fixture adaptation)
Manufacturing option
  • R: RoHS compliant
typically connected to production process and quality
Software Configuration -00: standard factory u-boot pre-programmed

-XX: custom version

If customers require custom SW deployed this section should be defined and agreed. Please contact technical support

Example[edit | edit source]

BORA Lite SOM code DBTD4111I0R-00

  • DBT - BORA Lite SOM module
  • D - XC7Z020 ARM Cortex-A9 866MHz - Speed grade -1
  • 4 - 16MB NOR Flash
  • 1 - 1GB DDR3
  • 1 - 1GB NAND flash
  • 1 - NOR boot
  • I - Industrial temperature range
  • 0 - PCB first version
  • R- RoHS manufacturing process
  • -00 - standard u-boot pre-programmed