Difference between revisions of "BORA Lite SOM/BORA Lite Hardware/Power and Reset/JTAG"
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| + | !colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History | ||
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| + | |style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|New documentation layout | ||
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{{:On_board_JTAG_connector_(BoraLite)}} | {{:On_board_JTAG_connector_(BoraLite)}} | ||
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Latest revision as of 15:41, 8 January 2024
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| History | |||
|---|---|---|---|
| Issue Date | Notes | ||
| 2020/12/01 | New documentation layout | ||
Info Box
|
On board JTAG connector[edit | edit source]
JTAG signals are routed to a dedicated connector (J2) on the BORA Lite PCB. The connector is placed on the top side of the PCB, at the upper-right corner (please see the picture below).
J2 - Connector's pinout[edit | edit source]
J2 footprint mates with Samtec FSI-110-03-G-S connector. The following table reports the connector's pinout:
| Pin# | Pin name | Function | Notes |
|---|---|---|---|
| 1 | DGND | - | - |
| 2 | JTAG_TCK | - | - |
| 3 | JTAG_TMS | - | - |
| 4 | JTAG_TDO | - | - |
| 5 | JTAG_TDI | - | - |
| 6 | FPGA_INIT_B | - | For further details, please refer to PL initialization signals |
| 7 | FPGA_PROGRAM_B | - | For further details, please refer to PL initialization signals
(10 kΩ pull-up resistor is already mounted on BORA module) |
| 8 | FPGA_DONE | - | For further details, please refer to PL initialization signals |
| 9 | D.N.C. | - | RESERVED |
| 10 | 3V3 | - | 3.3VIN enabled with BOARD_PGOOD |
