Difference between revisions of "AXEL ULite SOM/AXEL ULite Hardware/Power and Reset/Power Supply Unit (PSU) and recommended power-up sequence"
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== Power Supply Unit (PSU) and recommended power-up sequence == | == Power Supply Unit (PSU) and recommended power-up sequence == | ||
Implementing correct power-up sequence for i.MX6UL processors is not a trivial task because several power rails are involved. AXELULite SOM simplifies this task by embedding all the needed circuitry. The following picture shows a simplified block diagram of PSU/voltage monitoring circuitry: | Implementing correct power-up sequence for i.MX6UL processors is not a trivial task because several power rails are involved. AXELULite SOM simplifies this task by embedding all the needed circuitry. The following picture shows a simplified block diagram of PSU/voltage monitoring circuitry: | ||
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[[File:AxelLite-power-sequence.png | 800px]] | [[File:AxelLite-power-sequence.png | 800px]] | ||
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The PSU is composed of two main blocks: | The PSU is composed of two main blocks: | ||
* power management integrated circuit (PMIC NXP PF3000) | * power management integrated circuit (PMIC NXP PF3000) | ||
| − | * additional | + | * additional circuitry that completes PMIC functionalities. |
The PSU: | The PSU: | ||
| − | * generates the proper power-up sequence required by i.MX6UL processor | + | * generates the proper power-up sequence required by i.MX6UL processor, surrounding memories and peripherals |
* synchronizes the powering up of carrier board in order to prevent back power. | * synchronizes the powering up of carrier board in order to prevent back power. | ||
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The typical power-up sequence is the following: | The typical power-up sequence is the following: | ||
| − | # (optional) PMIC_LICELL is powered | + | # (optional) PMIC_LICELL is powered by a Lithium coin cell battery |
| + | #*iMX6UL SNVS domain is powered (VDD_SNVS_IN) | ||
# VIN_SOM main power supply rail is powered | # VIN_SOM main power supply rail is powered | ||
| + | #*iMX6UL SNVS domain is powered (VDD_SNVS_IN) | ||
# CPU_PORn (active-low) is driven low | # CPU_PORn (active-low) is driven low | ||
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# PMIC_PWRON signal is pulled-up (unless carrier board circuitry keeps this signal low for any reason) | # PMIC_PWRON signal is pulled-up (unless carrier board circuitry keeps this signal low for any reason) | ||
# PMIC transitions from OFF to ON state | # PMIC transitions from OFF to ON state | ||
| − | # PMIC initiates power-up sequence | + | # PMIC initiates power-up sequence as per iMX6UL requirements |
| − | # SOM_PGOOD signal is | + | # SOM_PGOOD signal is set ti logic '1'; this active-high signal indicates that SoM's I/O is powered. This signal can be used to manage carrier board power up sequence in order to prevent back powering (from SoM to carrier board or vice versa). Generally speaking, all the circuitry that interfaces SOM's I/O signals should be powered on when SOM_PGOOD turns to logic '1'. |
# CPU_PORn is released. | # CPU_PORn is released. | ||
| − | = | + | For further details, please refer to <ref name="PF3000">Freescale Semiconductor, PF3000 Advance Information - Power Management Integrated Circuit (PMIC) for i.MX 7 & i.MX 6SL/SX/UL</ref>, <ref name="IMX6ULIEC">Freescale Semiconductor, Data Sheet: Technical Data - i.MX 6UltraLite Applications Processors for Industrial Products</ref>. |
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| − | + | ==References== | |
| + | {{reflist}} | ||
Revision as of 08:00, 15 July 2016
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Contents
Introduction[edit | edit source]
AXELULite system-on-module (SOM for short) is powered by carrier board via VIN_SOM rail.
About voltage range, three supported configurations are available. These configurations are indicated by the value of the f field of the ordering code. The generic ordering code is in the form:
DA p l r n c f t sThe field f can assume the following values:
- 0, 1: power supply voltage range 3.135 - 3.465V (that is 3V3±5%)
- 2: power supply voltage range is 3.3 - 4.5V
- please note that this range can be widened by the use of an external MOSFET; for more details please refer to technical support
- 3: power supply voltage range is 3.25 - 3.465V (that us 3.3 +5%/-1.5%).
Since powering is strictly related to reset signals, reading of this page is highly recommended.
Power Supply Unit (PSU) and recommended power-up sequence[edit | edit source]
Implementing correct power-up sequence for i.MX6UL processors is not a trivial task because several power rails are involved. AXELULite SOM simplifies this task by embedding all the needed circuitry. The following picture shows a simplified block diagram of PSU/voltage monitoring circuitry:
The PSU is composed of two main blocks:
- power management integrated circuit (PMIC NXP PF3000)
- additional circuitry that completes PMIC functionalities.
The PSU:
- generates the proper power-up sequence required by i.MX6UL processor, surrounding memories and peripherals
- synchronizes the powering up of carrier board in order to prevent back power.
Power-up sequence[edit | edit source]
The typical power-up sequence is the following:
- (optional) PMIC_LICELL is powered by a Lithium coin cell battery
- iMX6UL SNVS domain is powered (VDD_SNVS_IN)
- VIN_SOM main power supply rail is powered
- iMX6UL SNVS domain is powered (VDD_SNVS_IN)
- CPU_PORn (active-low) is driven low
- PMIC_PWRON signal is pulled-up (unless carrier board circuitry keeps this signal low for any reason)
- PMIC transitions from OFF to ON state
- PMIC initiates power-up sequence as per iMX6UL requirements
- SOM_PGOOD signal is set ti logic '1'; this active-high signal indicates that SoM's I/O is powered. This signal can be used to manage carrier board power up sequence in order to prevent back powering (from SoM to carrier board or vice versa). Generally speaking, all the circuitry that interfaces SOM's I/O signals should be powered on when SOM_PGOOD turns to logic '1'.
- CPU_PORn is released.
For further details, please refer to [1], [2].
