Difference between revisions of "AXEL ULite SOM/AXEL ULite Hardware/Pinout Table"

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(→‎SODIMM ODD pins declaration)
(→‎SODIMM ODD pins declaration)
Line 64: Line 64:
  
 
{| class="wikitable" border="1"  
 
{| class="wikitable" border="1"  
−
| style="background:#f0f0f0;" align="center" |'''Pin'''
+
! latexfontsize="scriptsize" | Pin  
−
| style="background:#f0f0f0;" align="center" |'''Pin Name'''
+
! latexfontsize="scriptsize" | Pin Name
−
| style="background:#f0f0f0;" align="center" |'''Internal Connections'''
+
! latexfontsize="scriptsize" | Internal Connections  
−
| style="background:#f0f0f0;" align="center" |'''Ball/pin #'''
+
! latexfontsize="scriptsize" | Ball/pin #  
−
| style="background:#f0f0f0;" align="center" |'''Notes'''
+
! latexfontsize="scriptsize" | Notes
−
! colspan="2" |Alternative Functions
+
! colspan="2" latexfontsize="scriptsize" | Alternative Functions
 
|-
 
|-
 
| J2.1 ||DGND ||DGND ||||
 
| J2.1 ||DGND ||DGND ||||
Line 147: Line 147:
 
|
 
|
 
|-
 
|-
−
| J2.39 ||CSI_HSYNC||CPU.CSI_HSYNC||F3||
+
| rowspan="8" | J2.39  
−
|
+
| rowspan="8" |CSI_HSYNC
−
|
+
| rowspan="8" |CPU.CSI_HSYNC
 +
| rowspan="8" |F3
 +
| rowspan="8" |
 +
|Pin ALT-0
 +
|CSI_HSYNC
 +
|-
 +
|Pin ALT-1
 +
|USDHC2_CMD
 +
|-
 +
|Pin ALT-2
 +
|SIM1_PORT1_PD
 +
|-
 +
|Pin ALT-3
 +
|I2C2_SCL
 +
|-
 +
|Pin ALT-4
 +
|EIM_LBA_B
 +
|-
 +
|Pin ALT-5
 +
|GPIO4_IO20
 +
|-
 +
|Pin ALT-6
 +
|PWM8_OUT
 +
|-
 +
|Pin ALT-8
 +
|UART6_CTS_B
 
|-
 
|-
 
| J2.41 ||SNVS_TAMPER5||CPU.SNVS_TAMPER5||N8||
 
| J2.41 ||SNVS_TAMPER5||CPU.SNVS_TAMPER5||N8||
Line 171: Line 196:
 
|
 
|
 
|-
 
|-
−
| J2.51 ||CSI_PIXCLK||CPU.CSI_PIXCLK||E5||
+
| rowspan="8" | J2.51
−
|
+
| rowspan="8" |CSI_PIXCLK
−
|
+
| rowspan="8" |CPU.CSI_PIXCLK
 +
| rowspan="8" |E5
 +
| rowspan="8" |
 +
|Pin ALT-0
 +
|CSI_PIXCLK
 +
|-
 +
|Pin ALT-1
 +
|USDHC2_WP
 +
|-
 +
|Pin ALT-2
 +
|RAWNAND_CE3_B
 +
|-
 +
|Pin ALT-3
 +
|I2C1_SCL
 +
|-
 +
|Pin ALT-4
 +
|EIM_OE
 +
|-
 +
|Pin ALT-5
 +
|GPIO4_IO18
 +
|-
 +
|Pin ALT-6
 +
|SVNS_HP_VIO_5
 +
|-
 +
|Pin ALT-8
 +
|UART6_RX
 +
|-
 +
| rowspan="8" | J2.53
 +
| rowspan="8" |CSI_MCLK
 +
| rowspan="8" |CPU.CSI_MCLK
 +
| rowspan="8" |F5
 +
| rowspan="8" |
 +
|Pin ALT-0
 +
|CSI_MCLK
 +
|-
 +
|Pin ALT-1
 +
|USDHC2_CD_B
 +
|-
 +
|Pin ALT-2
 +
|RAWNAND_CE2_B
 +
|-
 +
|Pin ALT-3
 +
|I2C1_SDA
 +
|-
 +
|Pin ALT-4
 +
|EIM_CS0_B
 +
|-
 +
|Pin ALT-5
 +
|GPIO4_IO17
 +
|-
 +
|Pin ALT-6
 +
|SVNS_HP_VIO_5_CTL
 
|-
 
|-
−
| J2.53 ||CSI_MCLK||CPU.CSI_MCLK||F5||
+
|Pin ALT-8
−
|
+
|UART6_TX
−
|
 
 
|-
 
|-
 
| J2.55 ||PMIC_VSNVS||PMIC.VSNVS||34||
 
| J2.55 ||PMIC_VSNVS||PMIC.VSNVS||34||
Line 199: Line 274:
 
|
 
|
 
|-
 
|-
−
| J2.65 ||UART5_RX_DATA||CPU.UART5_RX_DATA||G13||
+
| rowspan="7" | J2.65
−
|
+
| rowspan="7" |UART5_RX_DATA
−
|
+
| rowspan="7" |CPU.UART5_RX_DATA
 +
| rowspan="7" |G13
 +
| rowspan="7" |
 +
|Pin ALT-0
 +
|UART5_RX
 +
|-
 +
|Pin ALT-1
 +
|ENET2_COL
 +
|-
 +
|Pin ALT-2
 +
|I2C2_SDA
 +
|-
 +
|Pin ALT-3
 +
|CSI_DATA15
 +
|-
 +
|Pin ALT-4
 +
|CSU_INT_DEB
 +
|-
 +
|Pin ALT-5
 +
|GPIO1_IO31
 +
|-
 +
|Pin ALT-8
 +
|ECSPI2_MISO
 +
|-
 +
| rowspan="7" |J2.67
 +
| rowspan="7" |UART5_TX_DATA
 +
| rowspan="7" |CPU.UART5_TX_DATA
 +
| rowspan="7" |F17
 +
| rowspan="7" |
 +
|Pin ALT-0
 +
|UART5_TX
 +
|-
 +
|Pin ALT-1
 +
|ENET2_CRS
 +
|-
 +
|Pin ALT-2
 +
|I2C2_SCL
 +
|-
 +
|Pin ALT-3
 +
|CSI_DATA14
 +
|-
 +
|Pin ALT-4
 +
|CSU_ALARM_AUT00
 +
|-
 +
|Pin ALT-5
 +
|GPIO1_IO30
 
|-
 
|-
−
| J2.67 ||UART5_TX_DATA||CPU.UART5_TX_DATA||F17||
+
|Pin ALT-8
−
|
+
|ECSPI2_MOSI
−
|
 
 
|-
 
|-
 
| J2.69 ||VLDO3||PMIC.VLDO3||20||
 
| J2.69 ||VLDO3||PMIC.VLDO3||20||
Line 219: Line 338:
 
|
 
|
 
|-
 
|-
−
| J2.75 ||SD1_DATA0||CPU.SD1_DATA0||B3||
+
| rowspan="7" |J2.75
−
|
+
| rowspan="7" |SD1_DATA0
−
|
+
| rowspan="7" |CPU.SD1_DATA0
 +
| rowspan="7" |B3
 +
| rowspan="7" |
 +
|Pin ALT-0
 +
|USDHC1_DATA0
 +
|-
 +
|Pin ALT-1
 +
|GPT2_COMPARE3
 +
|-
 +
|Pin ALT-2
 +
|SAI2_TX_SYNC
 +
|-
 +
|Pin ALT-3
 +
|FLEXCAN1_TX
 +
|-
 +
|Pin ALT-4
 +
|EIM_ADDR21
 +
|-
 +
|Pin ALT-5
 +
|GPIO2_IO18
 +
|-
 +
|Pin ALT-8
 +
|ANATOP_OTG1_ID
 +
|-
 +
| rowspan="7" |J2.77
 +
| rowspan="7" |SD1_DATA1
 +
| rowspan="7" |CPU.SD1_DATA1
 +
| rowspan="7" |B2
 +
| rowspan="7" |
 +
|Pin ALT-0
 +
|USDHC1_DATA1
 +
|-
 +
|Pin ALT-1
 +
|GPT2_CLK
 +
|-
 +
|Pin ALT-2
 +
|SAI2_TX_BCLK
 +
|-
 +
|Pin ALT-3
 +
|FLEXCAN1_RX
 +
|-
 +
|Pin ALT-4
 +
|EIM_ADDR22
 +
|-
 +
|Pin ALT-5
 +
|GPIO2_IO19
 +
|-
 +
|Pin ALT-8
 +
|USB2_OTG_PWR
 +
|-
 +
| rowspan="8" |J2.79
 +
| rowspan="8" |SD1_DATA2
 +
| rowspan="8" |CPU.SD1_DATA2
 +
| rowspan="8" |B1
 +
| rowspan="8" |
 +
|Pin ALT-0
 +
|USDHC1_DATA2
 +
|-
 +
|Pin ALT-1
 +
|GPT2_CAPTURE1
 +
|-
 +
|Pin ALT-2
 +
|SAI2_RX_DATA
 +
|-
 +
|Pin ALT-3
 +
|FLEXCAN2_TX
 +
|-
 +
|Pin ALT-4
 +
|EIM_ADDR23
 +
|-
 +
|Pin ALT-5
 +
|GPIO2_IO20
 +
|-
 +
|Pin ALT-6
 +
|CCM_CLK01
 +
|-
 +
|Pin ALT-8
 +
|USB2_OTG_OC
 +
|-
 +
| rowspan="8" |J2.81
 +
| rowspan="8" |SD1_DATA3
 +
| rowspan="8" |CPU.SD1_DATA3
 +
| rowspan="8" |A2
 +
| rowspan="8" |
 +
|Pin ALT-0
 +
|USDHC1_DATA3
 +
|-
 +
|Pin ALT-1
 +
|GPT2_CAPTURE2
 +
|-
 +
|Pin ALT-2
 +
|SAI2_TX_DATA
 +
|-
 +
|Pin ALT-3
 +
|FLEXCAN2_RX
 +
|-
 +
|Pin ALT-4
 +
|EIM_ADDR24
 +
|-
 +
|Pin ALT-5
 +
|GPIO2_IO21
 +
|-
 +
|Pin ALT-6
 +
|CCM_CLK02
 +
|-
 +
|Pin ALT-8
 +
|ANATOP_OTG2_ID
 +
|-
 +
| rowspan="8" |J2.83
 +
| rowspan="8" |SD1_CMD
 +
| rowspan="8" |CPU.SD1_CMD
 +
| rowspan="8" |C2
 +
| rowspan="8" |
 +
|Pin ALT-0
 +
|USDHC1_CMD
 +
|-
 +
|Pin ALT-1
 +
|GPT2_COMPARE1
 +
|-
 +
|Pin ALT-2
 +
|SAI2_RX_SYNC
 +
|-
 +
|Pin ALT-3
 +
|SPDIF_OUT
 +
|-
 +
|Pin ALT-4
 +
|EIM_ADDR19
 +
|-
 +
|Pin ALT-5
 +
|GPIO2_IO16
 +
|-
 +
|Pin ALT-6
 +
|SDMA_EXT_EVNET00
 +
|-
 +
|Pin ALT-8
 +
|USB_OTG1_PWR
 +
|-
 +
| rowspan="7" |J2.85
 +
| rowspan="7" |SD1_CLK
 +
| rowspan="7" |CPU.SD1_CLK
 +
| rowspan="7" |C1
 +
| rowspan="7" |
 +
|Pin ALT-0
 +
|USDHC1_CLK
 +
|-
 +
|Pin ALT-1
 +
|GPT2_COMPARE2
 
|-
 
|-
−
| J2.77 ||SD1_DATA1||CPU.SD1_DATA1||B2||
+
|Pin ALT-2
−
|
+
|SAI2_MCLK
−
|
 
 
|-
 
|-
−
| J2.79 ||SD1_DATA2||CPU.SD1_DATA2||B1||
+
|Pin ALT-3
−
|
+
|SPDIF_IN
−
|
 
 
|-
 
|-
−
| J2.81 ||SD1_DATA3||CPU.SD1_DATA3||A2||
+
|Pin ALT-4
−
|
+
|EIM_ADDR20
−
|
 
 
|-
 
|-
−
| J2.83 ||SD1_CMD||CPU.SD1_CMD||C2||
+
|Pin ALT-5
−
|
+
|GPIO2_IO17
−
|
 
 
|-
 
|-
−
| J2.85 ||SD1_CLK||CPU.SD1_CLK||C1||
+
|Pin ALT-8
−
|
+
|USB_OTG1_OC
−
|
 
 
|-
 
|-
 
| J2.87 ||DGND ||DGND ||||
 
| J2.87 ||DGND ||DGND ||||
Line 247: Line 507:
 
|
 
|
 
|-
 
|-
−
| J2.89 ||GPIO1_IO04||CPU.GPIO_IO04||M16||
+
| rowspan="7" |J2.89
−
|
+
| rowspan="7" |GPIO1_IO04
−
|
+
| rowspan="7" |CPU.GPIO1_IO04
 +
| rowspan="7" |M16
 +
| rowspan="7" |
 +
|Pin ALT-0
 +
|ENET1_REF_CLK1
 +
|-
 +
|Pin ALT-1
 +
|PWM3_OUT
 +
|-
 +
|Pin ALT-2
 +
|USB_OTG1_PWR
 +
|-
 +
|Pin ALT-4
 +
|USDHC1_RESET_B
 +
|-
 +
|Pin ALT-5
 +
|GPIO1_IO04
 +
|-
 +
|Pin ALT-6
 +
|ENET2_1588_EVENT0_IN
 +
|-
 +
|Pin ALT-8
 +
|UART5_TX
 +
|-
 +
| rowspan="7" |J2.91
 +
| rowspan="7" |GPIO1_IO05
 +
| rowspan="7" |CPU.GPIO1_IO05
 +
| rowspan="7" |M17
 +
| rowspan="7" |
 +
|Pin ALT-0
 +
|ENET2_REF_CLK2
 +
|-
 +
|Pin ALT-1
 +
|PWM4_OUT
 +
|-
 +
|Pin ALT-2
 +
|ANATOP_OTG2_ID
 +
|-
 +
|Pin ALT-4
 +
|USDHC1_VSELECT
 +
|-
 +
|Pin ALT-5
 +
|GPIO1_IO05
 +
|-
 +
|Pin ALT-6
 +
|ENET2_1588_EVENT0_OUT
 +
|-
 +
|Pin ALT-8
 +
|UART5_RX
 +
|-
 +
| rowspan="8" |J2.93
 +
| rowspan="8" |ENET2_RX_DATA1
 +
| rowspan="8" |CPU.ENET2_RX_DATA1
 +
| rowspan="8" |C16
 +
| rowspan="8" |
 +
|Pin ALT-0
 +
|ENET2_RDATA01
 +
|-
 +
|Pin ALT-1
 +
|UART6_RX
 +
|-
 +
|Pin ALT-2
 +
|SIM_PORT0_CLK
 +
|-
 +
|Pin ALT-3
 +
|I2C3_SDA
 +
|-
 +
|Pin ALT-4
 +
|ENET1_MDC
 +
|-
 +
|Pin ALT-5
 +
|GPIO2_IO09
 +
|-
 +
|Pin ALT-6
 +
|KPP_COL04
 +
|-
 +
|Pin ALT-8
 +
|USB_OTG1_OC
 +
|-
 +
| rowspan="8" |J2.95
 +
| rowspan="8" |ENET2_RX_DATA0
 +
| rowspan="8" |CPU.ENET2_RX_DATA0
 +
| rowspan="8" |C17
 +
| rowspan="8" |
 +
|Pin ALT-0
 +
|ENET2_RDATA00
 +
|-
 +
|Pin ALT-1
 +
|UART6_TX
 +
|-
 +
|Pin ALT-2
 +
|SIM_PORT0_TRXD
 +
|-
 +
|Pin ALT-3
 +
|I2C3_SCL
 +
|-
 +
|Pin ALT-4
 +
|ENET1_MDIO
 +
|-
 +
|Pin ALT-5
 +
|GPIO2_IO08
 +
|-
 +
|Pin ALT-6
 +
|KPP_ROW04
 +
|-
 +
|Pin ALT-8
 +
|USB_OTG1_PWR
 +
|-
 +
| rowspan="7" |J2.97
 +
| rowspan="7" |ENET2_TX_DATA0
 +
| rowspan="7" |CPU.ENET2_TX_DATA0
 +
| rowspan="7" |A15
 +
| rowspan="7" |
 +
|Pin ALT-0
 +
|ENET2_TX_DATA00
 +
|-
 +
|Pin ALT-1
 +
|UART7_RX
 +
|-
 +
|Pin ALT-2
 +
|SIM1_PORT0_SVEN
 +
|-
 +
|Pin ALT-3
 +
|I2C4_SDA
 +
|-
 +
|Pin ALT-4
 +
|EIM_EB_B02
 +
|-
 +
|Pin ALT-5
 +
|GPIO2_IO11
 +
|-
 +
|Pin ALT-6
 +
|KPP_COL05
 +
|-
 +
| rowspan="8" |J2.99
 +
| rowspan="8" |ENET2_RX_EN
 +
| rowspan="8" |CPU.ENET2_RX_EN
 +
| rowspan="8" |B17
 +
| rowspan="8" |
 +
|Pin ALT-0
 +
|ENET2_RX_EN
 +
|-
 +
|Pin ALT-1
 +
|UART7_TX
 +
|-
 +
|Pin ALT-2
 +
|SIM1_PORT0_RST_B
 +
|-
 +
|Pin ALT-3
 +
|I2C4_SCL
 +
|-
 +
|Pin ALT-4
 +
|EIM_ADDR26
 +
|-
 +
|Pin ALT-5
 +
|GPIO2_IO10
 +
|-
 +
|Pin ALT-6
 +
|KPP_ROW05
 +
|-
 +
|Pin ALT-8
 +
|ENET1_REF_CLK_25M
 +
|-
 +
| rowspan="8" |J2.101
 +
| rowspan="8" |ENET2_TX_CLK
 +
| rowspan="8" |CPU.ENET2_TX_CLK
 +
| rowspan="8" |D17
 +
| rowspan="8" |
 +
|Pin ALT-0
 +
|ENET2_TX_CLK
 +
|-
 +
|Pin ALT-1
 +
|UART8_CTS_B
 +
|-
 +
|Pin ALT-2
 +
|SIM2_PORT0_RST_B
 +
|-
 +
|Pin ALT-3
 +
|ECSPI4_MISO
 +
|-
 +
|Pin ALT-4
 +
|ENET2_REF_CLK2
 +
|-
 +
|Pin ALT-5
 +
|GPIO2_IO14
 +
|-
 +
|Pin ALT-6
 +
|KPP_ROW07
 +
|-
 +
|Pin ALT-8
 +
|ANATOP_OTG2_ID
 +
|-
 +
| rowspan="8" |J2.103
 +
| rowspan="8" |ENET2_RX_ER
 +
| rowspan="8" |CPU.ENET2_RX_ER
 +
| rowspan="8" |D16
 +
| rowspan="8" |
 +
|Pin ALT-0
 +
|ENET2_RX_ER
 +
|-
 +
|Pin ALT-1
 +
|UART8_RTS_B
 +
|-
 +
|Pin ALT-2
 +
|SIM2_PORT0_SVEN
 +
|-
 +
|Pin ALT-3
 +
|ECSPI4_SS0
 +
|-
 +
|Pin ALT-4
 +
|EIM_ADDR25
 +
|-
 +
|Pin ALT-5
 +
|GPIO2_IO15
 +
|-
 +
|Pin ALT-6
 +
|KPP_COL07
 +
|-
 +
|Pin ALT-8
 +
|WDOG1_WDOG_ANY
 +
|-
 +
| rowspan="8" |J2.105
 +
| rowspan="8" |ENET2_TX_EN
 +
| rowspan="8" |CPU.ENET2_TX_EN
 +
| rowspan="8" |B15
 +
| rowspan="8" |
 +
|Pin ALT-0
 +
|ENET2_TX_EN
 +
|-
 +
|Pin ALT-1
 +
|UART8_RX
 +
|-
 +
|Pin ALT-2
 +
|SIM2_PORT0_CLK
 +
|-
 +
|Pin ALT-3
 +
|ECSPI4_MOSI
 +
|-
 +
|Pin ALT-4
 +
|EIM_ACK_FREERUN
 +
|-
 +
|Pin ALT-5
 +
|GPIO2_IO13
 +
|-
 +
|Pin ALT-6
 +
|KPP_COL06
 
|-
 
|-
−
| J2.91 ||GPIO1_IO05||CPU.GPIO_IO05||M17||
+
|Pin ALT-8
−
|
+
|USB_OTG2_OC
−
|
 
 
|-
 
|-
−
| J2.93 ||ENET2_RX_DATA1||CPU.ENET2_RX_DATA1||C16||
+
| rowspan="8" |J2.107
−
|
+
| rowspan="8" |ENET2_TX_DATA1
−
|
+
| rowspan="8" |CPU.ENET2_TX_DATA1
 +
| rowspan="8" |A16
 +
| rowspan="8" |
 +
|Pin ALT-0
 +
|ENET2_TX_DATA01
 
|-
 
|-
−
| J2.95 ||ENET2_RX_DATA0||CPU.ENET2_RX_DATA0||C17||
+
|Pin ALT-1
−
|
+
|UART8_TX
−
|
 
 
|-
 
|-
−
| J2.97 ||ENET2_TX_DATA0||CPU.ENET2_TX_DATA0||A15||
+
|Pin ALT-2
−
|
+
|SIM2_PORT0_TRXD
−
|
 
 
|-
 
|-
−
| J2.99 ||ENET2_RX_EN||CPU.ENET2_RX_EN||B17||
+
|Pin ALT-3
−
|
+
|ECSPI4_SCLK
−
|
 
 
|-
 
|-
−
| J2.101 ||ENET2_TX_CLK||CPU.ENET2_TX_CLK||D17||
+
|Pin ALT-4
−
|
+
|EIM_EB_B03
−
|
 
 
|-
 
|-
−
| J2.103 ||ENET2_RX_ER||CPU.ENET2_RX_ER||D16||
+
|Pin ALT-5
−
|
+
|GPIO2_IO12
−
|
 
 
|-
 
|-
−
| J2.105 ||ENET2_TX_EN||CPU.ENET2_TX_EN||B15||
+
|Pin ALT-6
−
|
+
|KPP_ROW06
−
|
 
 
|-
 
|-
−
| J2.107 ||ENET2_TX_DATA1||CPU.ENET2_TX_DATA1||A16||
+
|Pin ALT-8
−
|
+
|USB_OTG2_PWR
−
|
 
 
|-
 
|-
 
| J2.109 ||DGND ||DGND ||||
 
| J2.109 ||DGND ||DGND ||||
Line 323: Line 824:
 
|
 
|
 
|-
 
|-
−
| J2.127 ||GPIO1_IO06||CPU.GPIO_IO06||K17||Internally connected to ethernet PHY (MDIO) with 1K ohm pull-up
+
| rowspan="9" |J2.127
−
|
+
| rowspan="9" |GPIO1_IO06
−
|
+
| rowspan="9" |CPU.GPIO1_IO06
 +
| rowspan="9" |K17
 +
| rowspan="9" |Internally connected to ethernet PHY (MDIO) with 1K ohm pull-up
 +
|Pin ALT-0
 +
|ENET1_MDIO
 +
|-
 +
|Pin ALT-1
 +
|ENET2_MDIO
 +
|-
 +
|Pin ALT-2
 +
|USB_OTG_PWR_WAKE
 +
|-
 +
|Pin ALT-3
 +
|CSI_MCLK
 +
|-
 +
|Pin ALT-4
 +
|USDHC2_WP
 +
|-
 +
|Pin ALT-5
 +
|GPIO1_IO16
 +
|-
 +
|Pin ALT-6
 +
|CCM_WAIT
 +
|-
 +
|Pin ALT-7
 +
|CCM_REF_EN_B
 +
|-
 +
|Pin ALT-8
 +
|UART1_CTS_B
 +
|-
 +
| rowspan="8" |J2.129
 +
| rowspan="8" |GPIO1_IO07
 +
| rowspan="8" |CPU.GPIO1_IO07
 +
| rowspan="8" |L16
 +
| rowspan="8" |Internally connected to ethernet PHY (MDC) with 1K ohm pull-up
 +
|Pin ALT-0
 +
|ENET1_MDC
 +
|-
 +
|Pin ALT-1
 +
|ENET2_MDC
 +
|-
 +
|Pin ALT-2
 +
|USB_OTG_HOST_MODE
 +
|-
 +
|Pin ALT-3
 +
|CSI_PXCLK
 +
|-
 +
|Pin ALT-4
 +
|USDHC2_CD_B
 +
|-
 +
|Pin ALT-5
 +
|GPIO1_IO17
 +
|-
 +
|Pin ALT-6
 +
|CCM_STOP
 
|-
 
|-
−
| J2.129 ||GPIO1_IO07||CPU.GPIO_IO07||L16||Internally connected to ethernet PHY (MDC) with 1K ohm pull-up
+
|Pin ALT-8
−
|
+
|UART1_RTS_B
−
|
 
 
|-
 
|-
 
| J2.131 ||DGND ||DGND ||||
 
| J2.131 ||DGND ||DGND ||||
Line 335: Line 889:
 
|
 
|
 
|-
 
|-
−
| J2.133 ||CSI_DATA04||CPU.CSI_DATA04||D4||Internally connected to NOR SPI flash
+
| rowspan="8" |J2.133
−
|
+
| rowspan="8" |CSI_DATA04
−
|
+
| rowspan="8" |CPU.CSI_DATA04
 +
| rowspan="8" |D4
 +
| rowspan="8" |Internally connected to NOR SPI flash
 +
|Pin ALT-0
 +
|CSI_DATA06
 +
|-
 +
|Pin ALT-1
 +
|USDHC2_DATA4
 +
|-
 +
|Pin ALT-2
 +
|SIM2_PORT1_CLK
 +
|-
 +
|Pin ALT-3
 +
|ECSPI1_SCLK
 +
|-
 +
|Pin ALT-4
 +
|EIM_AD04
 +
|-
 +
|Pin ALT-5
 +
|GPIO4_IO25
 +
|-
 +
|Pin ALT-6
 +
|SAI1_TX_SYNC
 +
|-
 +
|Pin ALT-8
 +
|USDHC1_WP
 +
|-
 +
| rowspan="8" |J2.135
 +
| rowspan="8" |CSI_DATA05
 +
| rowspan="8" |CPU.CSI_DATA05
 +
| rowspan="8" |D3
 +
| rowspan="8" |Internally connected to NOR SPI flash
 +
|Pin ALT-0
 +
|CSI_DATA07
 +
|-
 +
|Pin ALT-1
 +
|USDHC2_DATA5
 +
|-
 +
|Pin ALT-2
 +
|SIM2_PORT1_RST_B
 +
|-
 +
|Pin ALT-3
 +
|ECSPI1_SS0
 +
|-
 +
|Pin ALT-4
 +
|EIM_AD05
 +
|-
 +
|Pin ALT-5
 +
|GPIO4_IO26
 +
|-
 +
|Pin ALT-6
 +
|SAI1_TX_BCLK
 +
|-
 +
|Pin ALT-8
 +
|USDHC1_CD_B
 +
|-
 +
| rowspan="8" |J2.137
 +
| rowspan="8" |CSI_DATA07
 +
| rowspan="8" |CPU.CSI_DATA07
 +
| rowspan="8" |D2
 +
| rowspan="8" |Internally connected to NOR SPI flash
 +
|Pin ALT-0
 +
|CSI_DATA09
 +
|-
 +
|Pin ALT-1
 +
|USDHC2_DATA7
 +
|-
 +
|Pin ALT-2
 +
|SIM2_PORT1_TRXD
 +
|-
 +
|Pin ALT-3
 +
|ECSPI1_MISO
 +
|-
 +
|Pin ALT-4
 +
|EIM_AD07
 +
|-
 +
|Pin ALT-5
 +
|GPIO4_IO28
 +
|-
 +
|Pin ALT-6
 +
|SAI1_TX_DATA
 +
|-
 +
|Pin ALT-8
 +
|USDHC1_VSELECT
 +
|-
 +
| rowspan="8" |J2.139
 +
| rowspan="8" |CSI_DATA06
 +
| rowspan="8" |CPU.CSI_DATA06
 +
| rowspan="8" |D1
 +
| rowspan="8" |Internally connected to NOR SPI flash
 +
|Pin ALT-0
 +
|CSI_DATA08
 +
|-
 +
|Pin ALT-1
 +
|USDHC2_DATA6
 +
|-
 +
|Pin ALT-2
 +
|SIM2_PORT1_SVEN
 +
|-
 +
|Pin ALT-3
 +
|ECSPI1_MOSI
 +
|-
 +
|Pin ALT-4
 +
|EIM_AD06
 
|-
 
|-
−
| J2.135 ||CSI_DATA05||CPU.CSI_DATA05||D3||Internally connected to NOR SPI flash
+
|Pin ALT-5
−
|
+
|GPIO4_IO27
−
|
 
 
|-
 
|-
−
| J2.137 ||CSI_DATA07||CPU.CSI_DATA06||D2||Internally connected to NOR SPI flash
+
|Pin ALT-6
−
|
+
|SAI1_RX_DATA
−
|
 
 
|-
 
|-
−
| J2.139 ||CSI_DATA06||CPU.CSI_DATA07||D1||Internally connected to NOR SPI flash
+
|Pin ALT-8
−
|
+
|USDHC1_RESET_B
−
|
 
 
|-
 
|-
 
| J2.141 ||NVCC_ENET||CPU.NVCC_ENET||F13||
 
| J2.141 ||NVCC_ENET||CPU.NVCC_ENET||F13||
Line 367: Line 1,021:
 
|
 
|
 
|-
 
|-
−
| J2.149 ||UART4_RX_DATA||CPU.UART4_RX_DATA||G16||Internally connected to PMIC (used as I2C1 SDA)
+
| rowspan="7" |J2.149
−
|
+
| rowspan="7" |UART4_RX_DATA
−
|
+
| rowspan="7" |CPU.UART4_RX_DATA
 +
| rowspan="7" |G16
 +
| rowspan="7" |Internally connected to PMIC (used as I2C1 SDA)
 +
|Pin ALT-0
 +
|UART4_RX
 +
|-
 +
|Pin ALT-1
 +
|ENET2_TDATA03
 +
|-
 +
|Pin ALT-2
 +
|I2C1_SDA
 +
|-
 +
|Pin ALT-3
 +
|CSI_DATA13
 +
|-
 +
|Pin ALT-4
 +
|CSU_ALARM_AUT01
 +
|-
 +
|Pin ALT-5
 +
|GPIO1_IO29
 +
|-
 +
|Pin ALT-8
 +
|ECSPI2_SS0
 +
|-
 +
| rowspan="7" |J2.151
 +
| rowspan="7" |UART4_TX_DATA
 +
| rowspan="7" |CPU.UART4_TX_DATA
 +
| rowspan="7" |G17
 +
| rowspan="7" |Internally connected to PMIC (used as I2C1 SCL)
 +
|Pin ALT-0
 +
|UART4_TX
 +
|-
 +
|Pin ALT-1
 +
|ENET2_TDATA02
 +
|-
 +
|Pin ALT-2
 +
|I2C1_SCL
 +
|-
 +
|Pin ALT-3
 +
|CSI_DATA12
 +
|-
 +
|Pin ALT-4
 +
|CSU_ALARM_AUT02
 +
|-
 +
|Pin ALT-5
 +
|GPIO1_IO28
 
|-
 
|-
−
| J2.151 ||UART4_TX_DATA||CPU.UART4_TX_DATA||G17||Internally connected to PMIC (used as I2C1 SCL)
+
|Pin ALT-8
−
|
+
|ECSPI2_SCLK
−
|
 
 
|-
 
|-
 
| J2.153 ||DGND ||DGND ||||
 
| J2.153 ||DGND ||DGND ||||
Line 423: Line 1,121:
 
|
 
|
 
|-
 
|-
−
| J2.177 ||UART1_nRTS||CPU.UART1_nRTS||J14||
+
| rowspan="7" |J2.177
−
|
+
| rowspan="7" |UART1_RTS_B
−
|
+
| rowspan="7" |CPU.UART1_RTS_B
 +
| rowspan="7" |J14
 +
| rowspan="7" |
 +
|Pin ALT-0
 +
|UART1_RTS_B
 +
|-
 +
|Pin ALT-1
 +
|ENET1_TX_ER
 +
|-
 +
|Pin ALT-2
 +
|USDHC1_CD_B
 +
|-
 +
|Pin ALT-3
 +
|CSI_DATA05
 +
|-
 +
|Pin ALT-4
 +
|ENET2_1588_EVENT1_OUT
 +
|-
 +
|Pin ALT-5
 +
|GPIO1_IO19
 +
|-
 +
|Pin ALT-8
 +
|USDHC2_CD_B
 +
|-
 +
| rowspan="7" |J2.179
 +
| rowspan="7" |UART2_RTS_B
 +
| rowspan="7" |CPU.UART2_RTS_B
 +
| rowspan="7" |H14
 +
| rowspan="7" |
 +
|Pin ALT-0
 +
|UART2_RTS_B
 +
|-
 +
|Pin ALT-1
 +
|ENET1_COL
 +
|-
 +
|Pin ALT-2
 +
|FLEXCAN2_RX
 +
|-
 +
|Pin ALT-3
 +
|CSI_DATA09
 +
|-
 +
|Pin ALT-4
 +
|GPT1_COMPARE3
 +
|-
 +
|Pin ALT-5
 +
|GPIO1_IO23
 +
|-
 +
|Pin ALT-8
 +
|ECSPI3_MISO
 +
|-
 +
| rowspan="8" |J2.181
 +
| rowspan="8" |UART2_CTS_B
 +
| rowspan="8" |CPU.UART2_CTS_B
 +
| rowspan="8" |J15
 +
| rowspan="8" |
 +
|Pin ALT-0
 +
|UART2_CTS_B
 +
|-
 +
|Pin ALT-1
 +
|ENET1_CRS
 +
|-
 +
|Pin ALT-2
 +
|FLEXCAN2_TX
 +
|-
 +
|Pin ALT-3
 +
|CSI_DATA08
 +
|-
 +
|Pin ALT-4
 +
|GPT1_COMPARE2
 +
|-
 +
|Pin ALT-5
 +
|GPIO1_IO22
 +
|-
 +
|Pin ALT-7
 +
|SJC_DE_B
 +
|-
 +
|Pin ALT-8
 +
|ECSPI3_MOSI
 +
|-
 +
| rowspan="9" |J2.183
 +
| rowspan="9" |GPIO1_IO02
 +
| rowspan="9" |CPU.GPIO1_IO02
 +
| rowspan="9" |L14
 +
| rowspan="9" |
 +
|Pin ALT-0
 +
|I2C1_SCL
 +
|-
 +
|Pin ALT-1
 +
|GPT1_COMPARE2
 +
|-
 +
|Pin ALT-2
 +
|USB_OTG2_PWR
 +
|-
 +
|Pin ALT-3
 +
|ENET1_REF_CLK_25M
 +
|-
 +
|Pin ALT-4
 +
|USDHC1_WP
 +
|-
 +
|Pin ALT-5
 +
|GPIO1_IO02
 
|-
 
|-
−
| J2.179 ||UART2_nRTS||CPU.UART2_nRTS||H14||
+
|Pin ALT-6
−
|
+
|SDMA_EXT_EVENT00
−
|
 
 
|-
 
|-
−
| J2.181 ||UART2_nCTS||CPU.UART2_nCTS||J15||
+
|Pin ALT-7
−
|
+
|SRC_ANY_PU_RESET
−
|
 
 
|-
 
|-
−
| J2.183 ||GPIO1_IO02||CPU.GPIO_IO02||L14||
+
|Pin ALT-8
−
|
+
|UART1_TX
−
|
 
 
|-
 
|-
 
| J2.185 ||N.C.||||||Not connected. Leave this pin floating.
 
| J2.185 ||N.C.||||||Not connected. Leave this pin floating.
Line 443: Line 1,238:
 
|
 
|
 
|-
 
|-
−
| J2.187 ||UART1_TX_DATA||CPU.UART1_TX_DATA||K14||
+
| rowspan="7" |J2.187
−
|
+
| rowspan="7" |UART1_TX_DATA
−
|
+
| rowspan="7" |CPU.UART1_TX_DATA
 +
| rowspan="7" |K14
 +
| rowspan="7" |
 +
|Pin ALT-0
 +
|UART1_TX
 +
|-
 +
|Pin ALT-1
 +
|ENET1_RDATA02
 +
|-
 +
|Pin ALT-2
 +
|I2C3_SCL
 +
|-
 +
|Pin ALT-3
 +
|CSI_DATA02
 +
|-
 +
|Pin ALT-4
 +
|GPT1_COMPARE1
 +
|-
 +
|Pin ALT-5
 +
|GPIO1_IO16
 +
|-
 +
|Pin ALT-8
 +
|SPDIF_OUT
 +
|-
 +
|-
 +
| rowspan="7" |J2.189
 +
| rowspan="7" |UART1_RX_DATA
 +
| rowspan="7" |CPU.UART1_RX_DATA
 +
| rowspan="7" |K16
 +
| rowspan="7" |
 +
|Pin ALT-0
 +
|UART1_RX
 +
|-
 +
|Pin ALT-1
 +
|ENET1_RDATA03
 +
|-
 +
|Pin ALT-2
 +
|I2C3_SDA
 +
|-
 +
|Pin ALT-3
 +
|CSI_DATA03
 +
|-
 +
|Pin ALT-4
 +
|GPT1_CLK
 +
|-
 +
|Pin ALT-5
 +
|GPIO1_IO17
 +
|-
 +
|Pin ALT-8
 +
|SPDIF_IN
 +
|-
 +
| rowspan="8" |J2.191
 +
| rowspan="8" |UART3_TX_DATA
 +
| rowspan="8" |CPU.UART3_TX_DATA
 +
| rowspan="8" |H17
 +
| rowspan="8" |
 +
|Pin ALT-0
 +
|UART3_TX
 +
|-
 +
|Pin ALT-1
 +
|ENET2_RDATA02
 +
|-
 +
|Pin ALT-2
 +
|SIM1_PORT0_PD
 +
|-
 +
|Pin ALT-3
 +
|CSI_DATA01
 +
|-
 +
|Pin ALT-4
 +
|UART2_CTS_B
 +
|-
 +
|Pin ALT-5
 +
|GPIO1_IO24
 +
|-
 +
|Pin ALT-7
 +
|SJC_JTAG_ACT
 +
|-
 +
|Pin ALT-8
 +
|ANATOP_OTG1_ID
 +
|-
 +
| rowspan="7" |J2.193
 +
| rowspan="7" |UART3_RX_DATA
 +
| rowspan="7" |CPU.UART3_RX_DATA
 +
| rowspan="7" |H16
 +
| rowspan="7" |
 +
|Pin ALT-0
 +
|UART3_RX
 +
|-
 +
|Pin ALT-1
 +
|ENET2_RDATA03
 +
|-
 +
|Pin ALT-2
 +
|SIM2_PORT0_PD
 +
|-
 +
|Pin ALT-3
 +
|CSI_DATA00
 +
|-
 +
|Pin ALT-4
 +
|UART2_RTS_B
 +
|-
 +
|Pin ALT-5
 +
|GPIO1_IO25
 +
|-
 +
|Pin ALT-8
 +
|EPT1_OUT
 +
|-
 +
| rowspan="7" |J2.195
 +
| rowspan="7" |UART3_CTS_B
 +
| rowspan="7" |CPU.UART3_CTS_B
 +
| rowspan="7" |H15
 +
| rowspan="7" |
 +
|Pin ALT-0
 +
|UART3_CTS_B
 +
|-
 +
|Pin ALT-1
 +
|ENET2_RX_CLK
 +
|-
 +
|Pin ALT-2
 +
|FLEXCAN1_TX
 +
|-
 +
|Pin ALT-3
 +
|CSI_DATA10
 +
|-
 +
|Pin ALT-4
 +
|ENET1_1588_EVENT1_IN
 +
|-
 +
|Pin ALT-5
 +
|GPIO1_IO26
 +
|-
 +
|Pin ALT-8
 +
|EPIT2_OUT
 +
|-
 +
| rowspan="7" |J2.197
 +
| rowspan="7" |UART3_RTS_B
 +
| rowspan="7" |CPU.UART3_RTS_B
 +
| rowspan="7" |G14
 +
| rowspan="7" |
 +
|Pin ALT-0
 +
|UART3_RTS_B
 +
|-
 +
|Pin ALT-1
 +
|ENET2_TX_ER
 +
|-
 +
|Pin ALT-2
 +
|FLEXCAN1_RX
 +
|-
 +
|Pin ALT-3
 +
|CSI_DATA11
 +
|-
 +
|Pin ALT-4
 +
|ENET1_1588_EVENT1_OUT
 +
|-
 +
|Pin ALT-5
 +
|GPIO1_IO27
 +
|-
 +
|Pin ALT-8
 +
|WDOG1_WDOG_B
 +
|-
 +
| rowspan="8" |J2.199
 +
| rowspan="8" |GPIO1_IO03
 +
| rowspan="8" |CPU.GPIO1_IO03
 +
| rowspan="8" |L17
 +
| rowspan="8" |
 +
|Pin ALT-0
 +
|I2C1_SDA
 +
|-
 +
|Pin ALT-1
 +
|GPT1_COMPARE2
 +
|-
 +
|Pin ALT-2
 +
|USB_OTG2_OC
 +
|-
 +
|Pin ALT-4
 +
|USDHC1_CD_B
 +
|-
 +
|Pin ALT-5
 +
|GPIO1_IO03
 +
|-
 +
|Pin ALT-6
 +
|CCM_DI0_EXT_CLK
 +
|-
 +
|Pin ALT-7
 +
|SRC_TESTER_ACK
 +
|-
 +
|Pin ALT-8
 +
|UART1_RX
 
|-
 
|-
−
| J2.189 ||UART1_RX_DATA||CPU.UART1_RX_DATA||K16||
+
| rowspan="7" |J2.201
−
|
+
| rowspan="7" |UART1_CTS_B
−
|
+
| rowspan="7" |CPU.UART1_CTS_B
 +
| rowspan="7" |K15
 +
| rowspan="7" |
 +
|Pin ALT-0
 +
|UART1_CTS_B
 
|-
 
|-
−
| J2.191 ||UART3_TX_DATA||CPU.UART3_TX_DATA||H17||
+
|Pin ALT-1
−
|
+
|ENET1_RX_CLK
−
|
 
 
|-
 
|-
−
| J2.193 ||UART3_RX_DATA||CPU.UART3_RX_DATA||H16||
+
|Pin ALT-2
−
|
+
|USDHC1_WP
−
|
 
 
|-
 
|-
−
| J2.195 ||UART3_nCTS||CPU.UART3_nCTS||H15||
+
|Pin ALT-3
−
|
+
|CSI_DATA04
−
|
 
 
|-
 
|-
−
| J2.197 ||UART3_nRTS||CPU.UART3_nRTS||G14||
+
|Pin ALT-4
−
|
+
|ENET2_1588_EVENT1_IN
−
|
 
 
|-
 
|-
−
| J2.199 ||GPIO1_IO03||CPU.GPIO_IO03||L17||
+
|Pin ALT-5
−
|
+
|GPIO1_IO18
−
|
 
 
|-
 
|-
−
| J2.201 ||UART1_CTS_B||CPU.UART1_nCTS||K15||
+
|Pin ALT-8
−
|
+
|USDHC2_WP
−
|
 
 
|-
 
|-
 
| J2.203 ||DGND ||DGND ||||
 
| J2.203 ||DGND ||DGND ||||

Revision as of 14:28, 20 February 2024

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History
Issue Date Notes

2016/07/21

New documentation layout

2017/08/04

Fix PMIC and SVNS information

2017/09/25

Fix USB OTG pin signals

2021/02/22

Add connectors layout
2022/01/203 Minor changes




Connectors and Pinout Table[edit | edit source]

Connectors description[edit | edit source]

In the following table are described all available connectors integrated on AXEL ULite SOM:

Connector name Connector Type Notes Carrier board counterpart
J1 SODIMM DDR3 edge connector 204 pin TE 2-2013289-1 (http://www.te.com/usa-en/product-2-2013289-1.html)

The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to AXEL ULite pinout specifications. See the images below for reference:

AXEL ULite TOP view
AXEL ULite BOTTOM view

Pinout table naming conventions[edit | edit source]

This chapter contains the pinout description of the AXEL ULite SOM module grouped in two tables (odd and even pins) that report the pin mapping of the 204-pin SO-DIMM Axel ULite connector. Each row in the pinout tables contains the following information:

  • Pin: reference to the connector pin
  • Pin Name: pin (signal) name on the Axel ULite connectors
  • Internal connections: connections to the Axel ULite components
    • CPU.<x> : pin connected to CPU pad named <x>
    • PMIC.<x> : pin connected to the Power Manager IC
    • LAN.<x> : pin connected to the LAN PHY
  • Ball/pin #: Component ball/pin number connected to signal

SODIMM ODD pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Notes Alternative Functions
J2.1 DGND DGND
J2.3 3.3VIN INPUT VOLTAGE
J2.5 3.3VIN INPUT VOLTAGE
J2.7 3.3VIN INPUT VOLTAGE
J2.9 3.3VIN INPUT VOLTAGE
J2.11 DGND DGND
J2.13 ETH_LED1 LAN.LED0/PME_N1 23
J2.15 VDDA_ADC_3P3 Reference voltage for SOC's ADC. Nominal value is 3.0V.
J2.17 DGND DGND
J2.19 ETH_TX_P LAN.TXP 6
J2.21 ETH_TX_M LAN.TXM 5
J2.23 ETH_RX_P LAN.RXP 4
J2.25 ETH_RX_M LAN.RXM 3
J2.27 SNVS_TAMPER0 CPU.SNVS_TAMPER0 R10
J2.29 SNVS_TAMPER1 CPU.SNVS_TAMPER1 R9
J2.31 SNVS_TAMPER2 CPU.SNVS_TAMPER2 P11 Internally connected to ethernet PHY INT signal
J2.33 SNVS_TAMPER3 CPU.SNVS_TAMPER3 P10
J2.35 DGND DGND
J2.37 SNVS_TAMPER4 CPU.SNVS_TAMPER4 P9
J2.39 CSI_HSYNC CPU.CSI_HSYNC F3 Pin ALT-0 CSI_HSYNC
Pin ALT-1 USDHC2_CMD
Pin ALT-2 SIM1_PORT1_PD
Pin ALT-3 I2C2_SCL
Pin ALT-4 EIM_LBA_B
Pin ALT-5 GPIO4_IO20
Pin ALT-6 PWM8_OUT
Pin ALT-8 UART6_CTS_B
J2.41 SNVS_TAMPER5 CPU.SNVS_TAMPER5 N8
J2.43 SNVS_TAMPER6 CPU.SNVS_TAMPER6 N11
J2.45 SNVS_TAMPER7 CPU.SNVS_TAMPER7 N10
J2.47 SNVS_TAMPER8 CPU.SNVS_TAMPER8 N9
J2.49 SNVS_TAMPER9 CPU.SNVS_TAMPER9 R6
J2.51 CSI_PIXCLK CPU.CSI_PIXCLK E5 Pin ALT-0 CSI_PIXCLK
Pin ALT-1 USDHC2_WP
Pin ALT-2 RAWNAND_CE3_B
Pin ALT-3 I2C1_SCL
Pin ALT-4 EIM_OE
Pin ALT-5 GPIO4_IO18
Pin ALT-6 SVNS_HP_VIO_5
Pin ALT-8 UART6_RX
J2.53 CSI_MCLK CPU.CSI_MCLK F5 Pin ALT-0 CSI_MCLK
Pin ALT-1 USDHC2_CD_B
Pin ALT-2 RAWNAND_CE2_B
Pin ALT-3 I2C1_SDA
Pin ALT-4 EIM_CS0_B
Pin ALT-5 GPIO4_IO17
Pin ALT-6 SVNS_HP_VIO_5_CTL
Pin ALT-8 UART6_TX
J2.55 PMIC_VSNVS PMIC.VSNVS 34
J2.57 DGND DGND
J2.59 VPWR PMIC.VPWR 31
J2.61 VLDO2 PMIC.VLDO2 15
J2.63 VLDO2 PMIC.VLDO2 15
J2.65 UART5_RX_DATA CPU.UART5_RX_DATA G13 Pin ALT-0 UART5_RX
Pin ALT-1 ENET2_COL
Pin ALT-2 I2C2_SDA
Pin ALT-3 CSI_DATA15
Pin ALT-4 CSU_INT_DEB
Pin ALT-5 GPIO1_IO31
Pin ALT-8 ECSPI2_MISO
J2.67 UART5_TX_DATA CPU.UART5_TX_DATA F17 Pin ALT-0 UART5_TX
Pin ALT-1 ENET2_CRS
Pin ALT-2 I2C2_SCL
Pin ALT-3 CSI_DATA14
Pin ALT-4 CSU_ALARM_AUT00
Pin ALT-5 GPIO1_IO30
Pin ALT-8 ECSPI2_MOSI
J2.69 VLDO3 PMIC.VLDO3 20
J2.71 VLDO3 PMIC.VLDO3 20
J2.73 DGND DGND
J2.75 SD1_DATA0 CPU.SD1_DATA0 B3 Pin ALT-0 USDHC1_DATA0
Pin ALT-1 GPT2_COMPARE3
Pin ALT-2 SAI2_TX_SYNC
Pin ALT-3 FLEXCAN1_TX
Pin ALT-4 EIM_ADDR21
Pin ALT-5 GPIO2_IO18
Pin ALT-8 ANATOP_OTG1_ID
J2.77 SD1_DATA1 CPU.SD1_DATA1 B2 Pin ALT-0 USDHC1_DATA1
Pin ALT-1 GPT2_CLK
Pin ALT-2 SAI2_TX_BCLK
Pin ALT-3 FLEXCAN1_RX
Pin ALT-4 EIM_ADDR22
Pin ALT-5 GPIO2_IO19
Pin ALT-8 USB2_OTG_PWR
J2.79 SD1_DATA2 CPU.SD1_DATA2 B1 Pin ALT-0 USDHC1_DATA2
Pin ALT-1 GPT2_CAPTURE1
Pin ALT-2 SAI2_RX_DATA
Pin ALT-3 FLEXCAN2_TX
Pin ALT-4 EIM_ADDR23
Pin ALT-5 GPIO2_IO20
Pin ALT-6 CCM_CLK01
Pin ALT-8 USB2_OTG_OC
J2.81 SD1_DATA3 CPU.SD1_DATA3 A2 Pin ALT-0 USDHC1_DATA3
Pin ALT-1 GPT2_CAPTURE2
Pin ALT-2 SAI2_TX_DATA
Pin ALT-3 FLEXCAN2_RX
Pin ALT-4 EIM_ADDR24
Pin ALT-5 GPIO2_IO21
Pin ALT-6 CCM_CLK02
Pin ALT-8 ANATOP_OTG2_ID
J2.83 SD1_CMD CPU.SD1_CMD C2 Pin ALT-0 USDHC1_CMD
Pin ALT-1 GPT2_COMPARE1
Pin ALT-2 SAI2_RX_SYNC
Pin ALT-3 SPDIF_OUT
Pin ALT-4 EIM_ADDR19
Pin ALT-5 GPIO2_IO16
Pin ALT-6 SDMA_EXT_EVNET00
Pin ALT-8 USB_OTG1_PWR
J2.85 SD1_CLK CPU.SD1_CLK C1 Pin ALT-0 USDHC1_CLK
Pin ALT-1 GPT2_COMPARE2
Pin ALT-2 SAI2_MCLK
Pin ALT-3 SPDIF_IN
Pin ALT-4 EIM_ADDR20
Pin ALT-5 GPIO2_IO17
Pin ALT-8 USB_OTG1_OC
J2.87 DGND DGND
J2.89 GPIO1_IO04 CPU.GPIO1_IO04 M16 Pin ALT-0 ENET1_REF_CLK1
Pin ALT-1 PWM3_OUT
Pin ALT-2 USB_OTG1_PWR
Pin ALT-4 USDHC1_RESET_B
Pin ALT-5 GPIO1_IO04
Pin ALT-6 ENET2_1588_EVENT0_IN
Pin ALT-8 UART5_TX
J2.91 GPIO1_IO05 CPU.GPIO1_IO05 M17 Pin ALT-0 ENET2_REF_CLK2
Pin ALT-1 PWM4_OUT
Pin ALT-2 ANATOP_OTG2_ID
Pin ALT-4 USDHC1_VSELECT
Pin ALT-5 GPIO1_IO05
Pin ALT-6 ENET2_1588_EVENT0_OUT
Pin ALT-8 UART5_RX
J2.93 ENET2_RX_DATA1 CPU.ENET2_RX_DATA1 C16 Pin ALT-0 ENET2_RDATA01
Pin ALT-1 UART6_RX
Pin ALT-2 SIM_PORT0_CLK
Pin ALT-3 I2C3_SDA
Pin ALT-4 ENET1_MDC
Pin ALT-5 GPIO2_IO09
Pin ALT-6 KPP_COL04
Pin ALT-8 USB_OTG1_OC
J2.95 ENET2_RX_DATA0 CPU.ENET2_RX_DATA0 C17 Pin ALT-0 ENET2_RDATA00
Pin ALT-1 UART6_TX
Pin ALT-2 SIM_PORT0_TRXD
Pin ALT-3 I2C3_SCL
Pin ALT-4 ENET1_MDIO
Pin ALT-5 GPIO2_IO08
Pin ALT-6 KPP_ROW04
Pin ALT-8 USB_OTG1_PWR
J2.97 ENET2_TX_DATA0 CPU.ENET2_TX_DATA0 A15 Pin ALT-0 ENET2_TX_DATA00
Pin ALT-1 UART7_RX
Pin ALT-2 SIM1_PORT0_SVEN
Pin ALT-3 I2C4_SDA
Pin ALT-4 EIM_EB_B02
Pin ALT-5 GPIO2_IO11
Pin ALT-6 KPP_COL05
J2.99 ENET2_RX_EN CPU.ENET2_RX_EN B17 Pin ALT-0 ENET2_RX_EN
Pin ALT-1 UART7_TX
Pin ALT-2 SIM1_PORT0_RST_B
Pin ALT-3 I2C4_SCL
Pin ALT-4 EIM_ADDR26
Pin ALT-5 GPIO2_IO10
Pin ALT-6 KPP_ROW05
Pin ALT-8 ENET1_REF_CLK_25M
J2.101 ENET2_TX_CLK CPU.ENET2_TX_CLK D17 Pin ALT-0 ENET2_TX_CLK
Pin ALT-1 UART8_CTS_B
Pin ALT-2 SIM2_PORT0_RST_B
Pin ALT-3 ECSPI4_MISO
Pin ALT-4 ENET2_REF_CLK2
Pin ALT-5 GPIO2_IO14
Pin ALT-6 KPP_ROW07
Pin ALT-8 ANATOP_OTG2_ID
J2.103 ENET2_RX_ER CPU.ENET2_RX_ER D16 Pin ALT-0 ENET2_RX_ER
Pin ALT-1 UART8_RTS_B
Pin ALT-2 SIM2_PORT0_SVEN
Pin ALT-3 ECSPI4_SS0
Pin ALT-4 EIM_ADDR25
Pin ALT-5 GPIO2_IO15
Pin ALT-6 KPP_COL07
Pin ALT-8 WDOG1_WDOG_ANY
J2.105 ENET2_TX_EN CPU.ENET2_TX_EN B15 Pin ALT-0 ENET2_TX_EN
Pin ALT-1 UART8_RX
Pin ALT-2 SIM2_PORT0_CLK
Pin ALT-3 ECSPI4_MOSI
Pin ALT-4 EIM_ACK_FREERUN
Pin ALT-5 GPIO2_IO13
Pin ALT-6 KPP_COL06
Pin ALT-8 USB_OTG2_OC
J2.107 ENET2_TX_DATA1 CPU.ENET2_TX_DATA1 A16 Pin ALT-0 ENET2_TX_DATA01
Pin ALT-1 UART8_TX
Pin ALT-2 SIM2_PORT0_TRXD
Pin ALT-3 ECSPI4_SCLK
Pin ALT-4 EIM_EB_B03
Pin ALT-5 GPIO2_IO12
Pin ALT-6 KPP_ROW06
Pin ALT-8 USB_OTG2_PWR
J2.109 DGND DGND
J2.111 N.C. Not connected. Leave this pin floating.
J2.113 N.C. Not connected. Leave this pin floating.
J2.115 N.C. Not connected. Leave this pin floating.
J2.117 N.C. Not connected. Leave this pin floating.
J2.119 N.C. Not connected. Leave this pin floating.
J2.121 N.C. Not connected. Leave this pin floating.
J2.123 N.C. Not connected. Leave this pin floating.
J2.125 N.C. Not connected. Leave this pin floating.
J2.127 GPIO1_IO06 CPU.GPIO1_IO06 K17 Internally connected to ethernet PHY (MDIO) with 1K ohm pull-up Pin ALT-0 ENET1_MDIO
Pin ALT-1 ENET2_MDIO
Pin ALT-2 USB_OTG_PWR_WAKE
Pin ALT-3 CSI_MCLK
Pin ALT-4 USDHC2_WP
Pin ALT-5 GPIO1_IO16
Pin ALT-6 CCM_WAIT
Pin ALT-7 CCM_REF_EN_B
Pin ALT-8 UART1_CTS_B
J2.129 GPIO1_IO07 CPU.GPIO1_IO07 L16 Internally connected to ethernet PHY (MDC) with 1K ohm pull-up Pin ALT-0 ENET1_MDC
Pin ALT-1 ENET2_MDC
Pin ALT-2 USB_OTG_HOST_MODE
Pin ALT-3 CSI_PXCLK
Pin ALT-4 USDHC2_CD_B
Pin ALT-5 GPIO1_IO17
Pin ALT-6 CCM_STOP
Pin ALT-8 UART1_RTS_B
J2.131 DGND DGND
J2.133 CSI_DATA04 CPU.CSI_DATA04 D4 Internally connected to NOR SPI flash Pin ALT-0 CSI_DATA06
Pin ALT-1 USDHC2_DATA4
Pin ALT-2 SIM2_PORT1_CLK
Pin ALT-3 ECSPI1_SCLK
Pin ALT-4 EIM_AD04
Pin ALT-5 GPIO4_IO25
Pin ALT-6 SAI1_TX_SYNC
Pin ALT-8 USDHC1_WP
J2.135 CSI_DATA05 CPU.CSI_DATA05 D3 Internally connected to NOR SPI flash Pin ALT-0 CSI_DATA07
Pin ALT-1 USDHC2_DATA5
Pin ALT-2 SIM2_PORT1_RST_B
Pin ALT-3 ECSPI1_SS0
Pin ALT-4 EIM_AD05
Pin ALT-5 GPIO4_IO26
Pin ALT-6 SAI1_TX_BCLK
Pin ALT-8 USDHC1_CD_B
J2.137 CSI_DATA07 CPU.CSI_DATA07 D2 Internally connected to NOR SPI flash Pin ALT-0 CSI_DATA09
Pin ALT-1 USDHC2_DATA7
Pin ALT-2 SIM2_PORT1_TRXD
Pin ALT-3 ECSPI1_MISO
Pin ALT-4 EIM_AD07
Pin ALT-5 GPIO4_IO28
Pin ALT-6 SAI1_TX_DATA
Pin ALT-8 USDHC1_VSELECT
J2.139 CSI_DATA06 CPU.CSI_DATA06 D1 Internally connected to NOR SPI flash Pin ALT-0 CSI_DATA08
Pin ALT-1 USDHC2_DATA6
Pin ALT-2 SIM2_PORT1_SVEN
Pin ALT-3 ECSPI1_MOSI
Pin ALT-4 EIM_AD06
Pin ALT-5 GPIO4_IO27
Pin ALT-6 SAI1_RX_DATA
Pin ALT-8 USDHC1_RESET_B
J2.141 NVCC_ENET CPU.NVCC_ENET F13
J2.143 VDD_SNVS_IN CPU.VDD_SNVS_IN P12 This is SoC's power rail of the SNVS domain. Please note that some SOC's GPIOs belong to this power domain.
J2.145 N.C. Not connected. Leave this pin floating.
J2.147 N.C. Not connected. Leave this pin floating.
J2.149 UART4_RX_DATA CPU.UART4_RX_DATA G16 Internally connected to PMIC (used as I2C1 SDA) Pin ALT-0 UART4_RX
Pin ALT-1 ENET2_TDATA03
Pin ALT-2 I2C1_SDA
Pin ALT-3 CSI_DATA13
Pin ALT-4 CSU_ALARM_AUT01
Pin ALT-5 GPIO1_IO29
Pin ALT-8 ECSPI2_SS0
J2.151 UART4_TX_DATA CPU.UART4_TX_DATA G17 Internally connected to PMIC (used as I2C1 SCL) Pin ALT-0 UART4_TX
Pin ALT-1 ENET2_TDATA02
Pin ALT-2 I2C1_SCL
Pin ALT-3 CSI_DATA12
Pin ALT-4 CSU_ALARM_AUT02
Pin ALT-5 GPIO1_IO28
Pin ALT-8 ECSPI2_SCLK
J2.153 DGND DGND
J2.155 N.C. Not connected. Leave this pin floating.
J2.157 N.C. Not connected. Leave this pin floating.
J2.159 N.C. Not connected. Leave this pin floating.
J2.161 N.C. Not connected. Leave this pin floating.
J2.163 N.C. Not connected. Leave this pin floating.
J2.165 N.C. Not connected. Leave this pin floating.
J2.167 N.C. Not connected. Leave this pin floating.
J2.169 N.C. Not connected. Leave this pin floating.
J2.171 N.C. Not connected. Leave this pin floating.
J2.173 N.C. Not connected. Leave this pin floating.
J2.175 DGND DGND
J2.177 UART1_RTS_B CPU.UART1_RTS_B J14 Pin ALT-0 UART1_RTS_B
Pin ALT-1 ENET1_TX_ER
Pin ALT-2 USDHC1_CD_B
Pin ALT-3 CSI_DATA05
Pin ALT-4 ENET2_1588_EVENT1_OUT
Pin ALT-5 GPIO1_IO19
Pin ALT-8 USDHC2_CD_B
J2.179 UART2_RTS_B CPU.UART2_RTS_B H14 Pin ALT-0 UART2_RTS_B
Pin ALT-1 ENET1_COL
Pin ALT-2 FLEXCAN2_RX
Pin ALT-3 CSI_DATA09
Pin ALT-4 GPT1_COMPARE3
Pin ALT-5 GPIO1_IO23
Pin ALT-8 ECSPI3_MISO
J2.181 UART2_CTS_B CPU.UART2_CTS_B J15 Pin ALT-0 UART2_CTS_B
Pin ALT-1 ENET1_CRS
Pin ALT-2 FLEXCAN2_TX
Pin ALT-3 CSI_DATA08
Pin ALT-4 GPT1_COMPARE2
Pin ALT-5 GPIO1_IO22
Pin ALT-7 SJC_DE_B
Pin ALT-8 ECSPI3_MOSI
J2.183 GPIO1_IO02 CPU.GPIO1_IO02 L14 Pin ALT-0 I2C1_SCL
Pin ALT-1 GPT1_COMPARE2
Pin ALT-2 USB_OTG2_PWR
Pin ALT-3 ENET1_REF_CLK_25M
Pin ALT-4 USDHC1_WP
Pin ALT-5 GPIO1_IO02
Pin ALT-6 SDMA_EXT_EVENT00
Pin ALT-7 SRC_ANY_PU_RESET
Pin ALT-8 UART1_TX
J2.185 N.C. Not connected. Leave this pin floating.
J2.187 UART1_TX_DATA CPU.UART1_TX_DATA K14 Pin ALT-0 UART1_TX
Pin ALT-1 ENET1_RDATA02
Pin ALT-2 I2C3_SCL
Pin ALT-3 CSI_DATA02
Pin ALT-4 GPT1_COMPARE1
Pin ALT-5 GPIO1_IO16
Pin ALT-8 SPDIF_OUT
J2.189 UART1_RX_DATA CPU.UART1_RX_DATA K16 Pin ALT-0 UART1_RX
Pin ALT-1 ENET1_RDATA03
Pin ALT-2 I2C3_SDA
Pin ALT-3 CSI_DATA03
Pin ALT-4 GPT1_CLK
Pin ALT-5 GPIO1_IO17
Pin ALT-8 SPDIF_IN
J2.191 UART3_TX_DATA CPU.UART3_TX_DATA H17 Pin ALT-0 UART3_TX
Pin ALT-1 ENET2_RDATA02
Pin ALT-2 SIM1_PORT0_PD
Pin ALT-3 CSI_DATA01
Pin ALT-4 UART2_CTS_B
Pin ALT-5 GPIO1_IO24
Pin ALT-7 SJC_JTAG_ACT
Pin ALT-8 ANATOP_OTG1_ID
J2.193 UART3_RX_DATA CPU.UART3_RX_DATA H16 Pin ALT-0 UART3_RX
Pin ALT-1 ENET2_RDATA03
Pin ALT-2 SIM2_PORT0_PD
Pin ALT-3 CSI_DATA00
Pin ALT-4 UART2_RTS_B
Pin ALT-5 GPIO1_IO25
Pin ALT-8 EPT1_OUT
J2.195 UART3_CTS_B CPU.UART3_CTS_B H15 Pin ALT-0 UART3_CTS_B
Pin ALT-1 ENET2_RX_CLK
Pin ALT-2 FLEXCAN1_TX
Pin ALT-3 CSI_DATA10
Pin ALT-4 ENET1_1588_EVENT1_IN
Pin ALT-5 GPIO1_IO26
Pin ALT-8 EPIT2_OUT
J2.197 UART3_RTS_B CPU.UART3_RTS_B G14 Pin ALT-0 UART3_RTS_B
Pin ALT-1 ENET2_TX_ER
Pin ALT-2 FLEXCAN1_RX
Pin ALT-3 CSI_DATA11
Pin ALT-4 ENET1_1588_EVENT1_OUT
Pin ALT-5 GPIO1_IO27
Pin ALT-8 WDOG1_WDOG_B
J2.199 GPIO1_IO03 CPU.GPIO1_IO03 L17 Pin ALT-0 I2C1_SDA
Pin ALT-1 GPT1_COMPARE2
Pin ALT-2 USB_OTG2_OC
Pin ALT-4 USDHC1_CD_B
Pin ALT-5 GPIO1_IO03
Pin ALT-6 CCM_DI0_EXT_CLK
Pin ALT-7 SRC_TESTER_ACK
Pin ALT-8 UART1_RX
J2.201 UART1_CTS_B CPU.UART1_CTS_B K15 Pin ALT-0 UART1_CTS_B
Pin ALT-1 ENET1_RX_CLK
Pin ALT-2 USDHC1_WP
Pin ALT-3 CSI_DATA04
Pin ALT-4 ENET2_1588_EVENT1_IN
Pin ALT-5 GPIO1_IO18
Pin ALT-8 USDHC2_WP
J2.203 DGND DGND

SODIMM EVEN pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin #
J2.2 DGND DGND
J2.4 3.3VIN INPUT VOLTAGE
J2.6 3.3VIN INPUT VOLTAGE
J2.8 3.3VIN INPUT VOLTAGE
J2.10 3.3VIN INPUT VOLTAGE
J2.12 DGND DGND
J2.14 PMIC_LICELL PMIC.LICELL 36
J2.16 CPU_ONOFF CPU.CPU_ONOFF R8
J2.18 SOM_PGOOD Internally connected to 150K pull-down
J2.20 BOOT_MODE0 CPU.BOOT_MODE0 T10 Reset scheme (AXEL ULite)
J2.22 CPU_PORn CPU.PORn P8
J2.24 PMIC_PWRON PMIC.PWRON 48
J2.26 BOOT_MODE1 CPU.BOOT_MODE1 U10 Reset scheme (AXEL ULite)
J2.28 GPIO1_IO08 CPU.GPIO_IO08 N17 Reset scheme (AXEL ULite)#Handling_CPU-initiated_software_reset
J2.30 DGND DGND
J2.32 CPU_PMIC_STBY_REQ CPU.CCM_PMIC_STBY_REQ U9
J2.34 JTAG_TMS CPU.JTAG_TMS P14
J2.36 PMIC_LDOG PMIC.LDOG 30
J2.38 GPIO1_IO00 CPU.GPIO_IO00 K13
J2.40 PMIC_SNVS_OUT PMIC.SNVS_OUT 34 This is normally left open.
J2.42 UART2_TX_DATA CPU.UART2_TX_DATA J17
J2.44 UART2_RX_DATA CPU.UART2_RX_DATA J16
J2.46 CSI_VSYNC CPU.CSI_VSYNC F2
J2.48 GPIO1_IO01 CPU.GPIO_IO01 L15
J2.50 PMIC_5V PMIC.BST 37 PMIC 5V output (boost regulator)
J2.52 PMIC_5V PMIC.BST 37 PMIC 5V output (boost regulator)
J2.54 N.C. Not connected. Leave this pin floating.
J2.56 DGND DGND
J2.58 GPIO1_IO09 CPU.GPIO_IO09 M15
J2.60 N.C. Not connected. Leave this pin floating.
J2.62 JTAG_VREF CPU.JTAG_VREF Internally connected to 240 ohm pull-up to 3V3
J2.64 JTAG_MOD CPU.JTAG_MOD P15 Internally connected to 10K pull-down
J2.66 JTAG_TDI CPU.JTAG_TDI N16
J2.68 JTAG_nTRST CPU.JTAG_nTRST N14
J2.70 JTAG_TDO CPU.JTAG_TDO N15
J2.72 JTAG_TCK CPU.JTAG_TCK M14
J2.74 CSI_DATA00 CPU.CSI_DATA00 E4
J2.76 CSI_DATA02 CPU.CSI_DATA02 E2
J2.78 CSI_DATA03 CPU.CSI_DATA03 E1
J2.80 CSI_DATA01 CPU.CSI_DATA01 E3
J2.82 DGND DGND
J2.84 NAND_READY# CPU.NAND_READY A3 Internally connected to NAND flash
J2.86 NAND_CLE CPU.NAND_CLE A4 Internally connected to NAND flash
J2.88 NAND_ALE CPU.NAND_ALE B4 Internally connected to NAND flash
J2.90 NAND_RE# CPU.NAND_RE D8 Internally connected to NAND flash
J2.92 NAND_WE# CPU.NAND_WE C8 Internally connected to NAND flash
J2.94 NAND_WP# CPU.NAND_WP D5 Internally connected to NAND flash
J2.96 NAND_CS0# CPU.NAND_CE0 C5 Internally connected to NAND flash
J2.98 NAND_CS1# CPU.NAND_CE1 B5 Internally connected to NAND flash
J2.100 DGND DGND
J2.102 NAND_DQS CPU.NAND_DQS E6 Internally connected to NAND flash
J2.104 NAND_DATA00 CPU.NAND_DATA00 D7 Internally connected to NAND flash
J2.106 NAND_DATA01 CPU.NAND_DATA01 B7 Internally connected to NAND flash
J2.108 NAND_DATA02 CPU.NAND_DATA02 A7 Internally connected to NAND flash
J2.110 NAND_DATA03 CPU.NAND_DATA03 D6 Internally connected to NAND flash
J2.112 NAND_DATA04 CPU.NAND_DATA04 C6 Internally connected to NAND flash
J2.114 NAND_DATA05 CPU.NAND_DATA05 B6 Internally connected to NAND flash
J2.116 NAND_DATA06 CPU.NAND_DATA06 A6 Internally connected to NAND flash
J2.118 NAND_DATA07 CPU.NAND_DATA07 A5 Internally connected to NAND flash
J2.120 MEM_WPn MEM_WPn
J2.122 DGND DGND
J2.124 LCD_DATA_EN CPU.LCD_ENABLE B8
J2.126 LCD_RESET CPU.LCD_RESET E9
J2.128 LCD_VSYNC CPU.LCD_VSYNC C9
J2.130 LCD_HSYNC CPU.LCD_HSYNC D9
J2.132 LCD_CLK CPU.LCD_CLK A8
J2.134 LCD_DATA00 CPU.LCD_DATA00 B9
J2.136 LCD_DATA01 CPU.LCD_DATA01 A9
J2.138 LCD_DATA02 CPU.LCD_DATA02 E10
J2.140 LCD_DATA03 CPU.LCD_DATA03 D10
J2.142 LCD_DATA04 CPU.LCD_DATA04 C10
J2.144 LCD_DATA05 CPU.LCD_DATA05 B10
J2.146 DGND
J2.148 LCD_DATA06 CPU.LCD_DATA06 A10
J2.150 LCD_DATA07 CPU.LCD_DATA07 D11
J2.152 LCD_DATA08 CPU.LCD_DATA08 B11
J2.154 LCD_DATA09 CPU.LCD_DATA09 A11
J2.156 LCD_DATA10 CPU.LCD_DATA10 E12
J2.158 LCD_DATA11 CPU.LCD_DATA11 D12
J2.160 LCD_DATA12 CPU.LCD_DATA12 C12
J2.162 LCD_DATA13 CPU.LCD_DATA13 B12
J2.164 DGND
J2.166 LCD_DATA14 CPU.LCD_DATA14 A12
J2.168 LCD_DATA15 CPU.LCD_DATA15 D13
J2.170 LCD_DATA16 CPU.LCD_DATA16 C13
J2.172 LCD_DATA17 CPU.LCD_DATA17 B13
J2.174 LCD_DATA18 CPU.LCD_DATA18 A13
J2.176 LCD_DATA19 CPU.LCD_DATA19 D14
J2.178 LCD_DATA20 CPU.LCD_DATA20 C14
J2.180 LCD_DATA21 CPU.LCD_DATA21 B14
J2.182 LCD_DATA22 CPU.LCD_DATA22 A14
J2.184 LCD_DATA23 CPU.LCD_DATA23 B16
J2.186 USB_OTG2_VBUS CPU.USB_OTG2_VBUS U12
J2.188 USB_OTG1_VBUS CPU.USB_OTG1_VBUS T12
J2.190 DGND DGND
J2.192 N.C. Not connected. Leave this pin floating.
J2.194 USB_OTG1_CHD# CPU.USB_OTG1_CHD U16
J2.196 USB_OTG2_DN CPU.USB_OTG2_DN T13
J2.198 USB_OTG2_DP CPU.USB_OTG2_DP U13
J2.200 USB_OTG1_DP CPU.USB_OTG1_DP T15
J2.202 USB_OTG1_DN CPU.USB_OTG1_DN U15
J2.204 DGND DGND
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