Difference between revisions of "AXEL Lite SOM/AXEL Lite Hardware/Power and Reset/System boot"
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* once it is satisfied, it executes the boot code | * once it is satisfied, it executes the boot code | ||
| − | == Boot options == | + | === Boot options === |
Two options are available related to system boot. They are identified by the ''Boot field'' of the ordering code as follows: | Two options are available related to system boot. They are identified by the ''Boot field'' of the ordering code as follows: | ||
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In any case, boot process is managed by on-chip boot ROM code that is described in detail in processor's Reference Manual. | In any case, boot process is managed by on-chip boot ROM code that is described in detail in processor's Reference Manual. | ||
| − | === SPI NOR / SD option === | + | ==== SPI NOR / SD option ==== |
Selection of primary boot device is determined by the BOOT_MODE_SEL signal as follows: | Selection of primary boot device is determined by the BOOT_MODE_SEL signal as follows: | ||
* BOOT_MODE_SEL = 0 | * BOOT_MODE_SEL = 0 | ||
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** in case no valid image is found in NOR flash, boot ROM shall enable USB serial download mode automatically | ** in case no valid image is found in NOR flash, boot ROM shall enable USB serial download mode automatically | ||
| − | === NAND / SD option === | + | ==== NAND / SD option ==== |
Selection of primary boot device is determined by the BOOT_MODE_SEL signal as follows: | Selection of primary boot device is determined by the BOOT_MODE_SEL signal as follows: | ||
* BOOT_MODE_SEL = 0 | * BOOT_MODE_SEL = 0 | ||
Revision as of 13:48, 29 August 2023
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| 11/11/2021 | Minor changes | ||
| 29/08/2023 | Minor changes | ||
Contents
System boot[edit | edit source]
The boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM core to begin execution starting from the on-chip boot ROM. The boot ROM:
- determines whether the boot is secure or non-secure
- performs some initialization of the system and clean-ups
- reads the mode pins to determine the primary boot device
- once it is satisfied, it executes the boot code
Boot options[edit | edit source]
Two options are available related to system boot. They are identified by the Boot field of the ordering code as follows:
- Boot field = 0 (SOM code: DXLxxxx0xxR): "SPI NOR / SD" option
- Boot field = 1 (SOM code: DXLxxxx1xxR): "NAND / SD" option
For both options, the selection of the primary boot device is determined by the BOOT_MODE_SEL signal as described in the following sections. BOOT_MODE_SEL is latched when processor reset is released.
In any case, boot process is managed by on-chip boot ROM code that is described in detail in processor's Reference Manual.
SPI NOR / SD option[edit | edit source]
Selection of primary boot device is determined by the BOOT_MODE_SEL signal as follows:
- BOOT_MODE_SEL = 0
- primary boot device is SD1
- boot ROM will try to boot a valid image from the SD card first, and then from the SPI NOR. In case no valid image is found, boot ROM shall enable USB serial download mode automatically
- BOOT_MODE_SEL = 1 or floating
- primary boot device is SPI NOR flash connected to eCSPI1
- in case no valid image is found in NOR flash, boot ROM shall enable USB serial download mode automatically
NAND / SD option[edit | edit source]
Selection of primary boot device is determined by the BOOT_MODE_SEL signal as follows:
- BOOT_MODE_SEL = 0
- primary boot device is SD1
- in case no valid image is found in SD card, boot ROM shall enable USB serial download mode automatically
- BOOT_MODE_SEL = 1 or floating
- primary boot device is NAND flash
- in case no valid image is found in NAND flash, boot ROM shall enable USB serial download mode automatically
Important note for DualLite/Solo based products (manufacture mode management)[edit | edit source]
When Dual Lite or Solo processor are used, GPIO_1 and GPIO_4 signals need to be kept high during bootstrap stage in order to prevent the intervention of bootrom's manufacture mode. Bootstrap stage has to be intended as the time elapsing between the release of hardware reset (CPU_PORn) and the execution of the first instruction of user code (typically this is the reset vector of U-Boot boot loader). Please note that, in case GPIO_1 signal is used to implement software reset circuit, it is high during bootstrap stage by design.
