Difference between revisions of "AXEL Lite SOM/AXEL Lite Hardware/Peripherals/MIPI"
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<section end=History/> | <section end=History/> | ||
| + | __FORCETOC__ | ||
<section begin=Body/> | <section begin=Body/> | ||
==Peripheral MIPI == | ==Peripheral MIPI == | ||
| − | + | The CSI-2 Host Controller is a digital core that implements all protocol functions defined in the MIPI CSI-2 Specification, providing an interface between the System and the MIPI | |
| − | + | D-PHY, allowing the communication with a MIPI CSI-2 compliant Camera Sensor | |
=== Description === | === Description === | ||
| − | The MIPI interface available on AXEL Lite is based on | + | The MIPI interface available on AXEL Lite is based on i.MX6 SoC and support the following features: |
| + | * Compliant with MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2), Version 1.00 - 29 November 2005 | ||
| + | * Interface with MIPI D-PHY following PHY Protocol Interface (PPI), as defined in MIPI Alliance Specification for D-PHY, Version 1.00.00 - 14 May 2009 | ||
| + | * Supports up to 2 (S/DL) and 4 (D/Q) D-PHY Rx Data Lanes | ||
| + | * Dynamically configurable multi-lane merging | ||
| + | * Long and Short packet decoding | ||
| + | * Timing accurate signaling of Frame and Line synchronization packets | ||
| + | * Support for several frame formats such as: | ||
| + | ** General Frame or Digital Interlaced Video with or without accurate sync timing | ||
| + | ** Data type (Packet or Frame level) and Virtual Channel interleaving | ||
| + | * 32-bit Image Data Interface delivering data formatted as recommended in CSI-2 Specification | ||
| + | * Supports all primary and secondary data formats: | ||
| + | ** RGB, YUV and RAW color space definitions | ||
| + | ** From 24-bit down to 6-bit per pixel | ||
| + | ** Generic or user-defined byte-based data types | ||
| + | * Error detection and correction: PHY, Packet, Line, Frame | ||
| + | |||
| + | === Camera ports === | ||
| + | The MIPI CSI-2 Serial port supports the following standards and features: | ||
| + | |||
| + | ==== i.MX 6Solo/6DualLite ==== | ||
| − | + | * Supporting from 80 Mbps to 1 Gbps speed per data lane | |
| + | * CSI-2 Receiver core can manage one clock lane and up to two lanes | ||
| − | + | ==== i.MX 6Dual/6Quad ==== | |
| − | * Support | + | * Support up to 1Gbps per lane in 1/2/3-lane mode and up to 800 Mbps/lane in 4-lane mode |
| − | * | + | * CSI-2 Receiver core can manage one clock lane and up to four data lanes |
| − | |||
===Pin mapping=== | ===Pin mapping=== | ||
Latest revision as of 17:16, 8 January 2024
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Contents
Peripheral MIPI[edit | edit source]
The CSI-2 Host Controller is a digital core that implements all protocol functions defined in the MIPI CSI-2 Specification, providing an interface between the System and the MIPI D-PHY, allowing the communication with a MIPI CSI-2 compliant Camera Sensor
Description[edit | edit source]
The MIPI interface available on AXEL Lite is based on i.MX6 SoC and support the following features:
- Compliant with MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2), Version 1.00 - 29 November 2005
- Interface with MIPI D-PHY following PHY Protocol Interface (PPI), as defined in MIPI Alliance Specification for D-PHY, Version 1.00.00 - 14 May 2009
- Supports up to 2 (S/DL) and 4 (D/Q) D-PHY Rx Data Lanes
- Dynamically configurable multi-lane merging
- Long and Short packet decoding
- Timing accurate signaling of Frame and Line synchronization packets
- Support for several frame formats such as:
- General Frame or Digital Interlaced Video with or without accurate sync timing
- Data type (Packet or Frame level) and Virtual Channel interleaving
- 32-bit Image Data Interface delivering data formatted as recommended in CSI-2 Specification
- Supports all primary and secondary data formats:
- RGB, YUV and RAW color space definitions
- From 24-bit down to 6-bit per pixel
- Generic or user-defined byte-based data types
- Error detection and correction: PHY, Packet, Line, Frame
Camera ports[edit | edit source]
The MIPI CSI-2 Serial port supports the following standards and features:
i.MX 6Solo/6DualLite[edit | edit source]
- Supporting from 80 Mbps to 1 Gbps speed per data lane
- CSI-2 Receiver core can manage one clock lane and up to two lanes
i.MX 6Dual/6Quad[edit | edit source]
- Support up to 1Gbps per lane in 1/2/3-lane mode and up to 800 Mbps/lane in 4-lane mode
- CSI-2 Receiver core can manage one clock lane and up to four data lanes
Pin mapping[edit | edit source]
The Pin mapping is described in the Pinout table section
