Difference between revisions of "AXEL Lite SOM/AXEL Lite Hardware/Peripherals/MIPI"
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=== Description === | === Description === | ||
| − | The MIPI interface available on AXEL Lite is based on | + | The MIPI interface available on AXEL Lite is based on i.MX6 SoC. |
| − | The MIPI port supports the following standards and features: | + | === Camera ports === |
| + | The MIPI CSI-2 Serial port supports the following standards and features: | ||
| − | * | + | ==== i.MX 6Solo/6DualLite ==== |
| − | * Support | + | |
| − | * | + | * Supporting from 80 Mbps to 1 Gbps speed per data lane |
| − | + | * CSI-2 Receiver core can manage one clock lane and up to two lanes | |
| + | |||
| + | ==== i.MX 6Dual/6Quad ==== | ||
| + | * Support up to 1Gbps per lane in 1/2/3-lane mode and up to 800 Mbps/lane in 4-lane mode | ||
| + | * CSI-2 Receiver core can manage one clock lane and up to four data lanes | ||
===Pin mapping=== | ===Pin mapping=== | ||
Revision as of 14:06, 7 October 2020
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Contents
Peripheral MIPI[edit | edit source]
TBD: sostituire le sezioni con le informazioni sull'uso della periferica Nell'esempio di seguito c'è la descrizione dell'interfaccia HDMI
Description[edit | edit source]
The MIPI interface available on AXEL Lite is based on i.MX6 SoC.
Camera ports[edit | edit source]
The MIPI CSI-2 Serial port supports the following standards and features:
i.MX 6Solo/6DualLite[edit | edit source]
- Supporting from 80 Mbps to 1 Gbps speed per data lane
- CSI-2 Receiver core can manage one clock lane and up to two lanes
i.MX 6Dual/6Quad[edit | edit source]
- Support up to 1Gbps per lane in 1/2/3-lane mode and up to 800 Mbps/lane in 4-lane mode
- CSI-2 Receiver core can manage one clock lane and up to four data lanes
Pin mapping[edit | edit source]
The Pin mapping is described in the Pinout table section
