Difference between revisions of "AURA SOM/AURA Hardware/Power and Reset/System boot"
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| − | !colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History | + | ! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History |
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| − | [ | + | This page illustrates the characteristics of the AURA's boot subsystem. Reading of the chapter ''System Boot'' of the ''i.MX 93 Applications Processor Reference Manual'' is highly recommended [1], though. i.MX93 SOC features several options in terms of booting. Such options are detailed in that document. |
| + | It is worth remembering that, by default, AURA supports ''Single Boot'' modes (i.e. the Cortex-A55 is the boot core) as detailed in the rest of the document. Other options are available on-demand, however, allowing to implement different configurations. DAVE Embedded Systems' team is available for additional information on this matter. If necessary, please contact [mailto:sales@dave.eu sales@dave.eu].<section end="History" />__FORCETOC__<section begin="Body" /> | ||
== System boot == | == System boot == | ||
| − | The boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM core to begin execution starting from the on-chip boot ROM. The boot ROM: | + | The boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM Cortex-A55 core to begin execution starting from the on-chip boot ROM. The boot ROM: |
* determines whether the boot is secure or non-secure | * determines whether the boot is secure or non-secure | ||
* performs some initialization of the system and clean-ups | * performs some initialization of the system and clean-ups | ||
| Line 26: | Line 24: | ||
=== Boot options === | === Boot options === | ||
| − | + | The default primary boot device is defined at the factory and identified by the 'Boot Mode' field of the ordering code as follows: | |
* 0: SPI NOR / SD option (SOM code: DAUxxx0xxxxR) | * 0: SPI NOR / SD option (SOM code: DAUxxx0xxxxR) | ||
| − | * 1: eMMC / SD option (SOM code: | + | * 1: eMMC / SD option (SOM code: DAUxxx1xxxxR) |
| − | * 2: SPI NAND / SD option (SOM code: | + | * 2: SPI NAND / SD option (SOM code: DAUxxx2xxxxR) |
| − | For both options | + | For both options an alternative primary boot from SD/MMC card is provided, selectable by driving low the BOOT_MODE_SEL signal. Bootable SD/MMC card connects via the SD2 (USDHC2) bus. |
| − | In any case, boot process is managed by on-chip boot ROM code that is described in detail in processor's Reference Manual. | + | All boot modes provide 'single boot' mode, meaning that the Cortex-A55 is the first core to boot. In any case, boot process is managed by on-chip boot ROM code that is described in detail in processor's Reference Manual. |
| − | + | {| class="wikitable" | |
| − | + | !Ordering code 'Boot Mode' fileld | |
| − | + | !BOOT_MODE_SEL | |
| − | + | !Primary boot device | |
| − | + | |- | |
| − | + | | rowspan="2" |0 | |
| − | + | |0 | |
| − | + | |SD/MMC card on USDHC2 | |
| − | + | |- | |
| + | |1 | ||
| + | |FlexSPI NOR on FLEXSPI1 | ||
| + | |- | ||
| + | | rowspan="2" |1 | ||
| + | |0 | ||
| + | |SD/MMC card on USDHC2 | ||
| + | |- | ||
| + | |1 | ||
| + | |eMMC on USDHC1 | ||
| + | |- | ||
| + | | rowspan="2" |2 | ||
| + | |0 | ||
| + | |SD/MMC card on USDHC2 | ||
| + | |- | ||
| + | |1 | ||
| + | |FlexSPI NAND on FLEXSPI1 | ||
| + | |} | ||
| − | === | + | === Note on boot signals === |
| − | + | * BOOT_MODE_SEL is latched when processor reset CPU_PORn is released. Inside the SOM, BOOT_MODE_SEL is pulled-up with 10 kohm. | |
| − | * BOOT_MODE_SEL | + | * The iMX93x SoC uses some GPIOs to read the boot configuration set on the SOM: for this reason the SOM's ports UART1_TXD, UART2_TXD, SAI1_TXFS and SAI1_TXD0 are floating (high impedance) while CPU_PORn signal is low. |
| − | + | [[File:AURA-boot-opt.png | 800px]] | |
| − | |||
| − | |||
| − | * | ||
| − | |||
| − | ==== | + | === Note on boot === |
| − | + | In case no valid image is found in primary boot device, boot ROM shall enable USB serial download mode automatically on USB OTG1. | |
| − | |||
| − | |||
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===Important note for ''manufacture mode'' management=== | ===Important note for ''manufacture mode'' management=== | ||
| Line 70: | Line 75: | ||
Bootstrap stage has to be intended as the time elapsing between the release of hardware reset (CPU_PORn) and the execution of the first instruction of user code (typically this is the reset vector of U-Boot boot loader). | Bootstrap stage has to be intended as the time elapsing between the release of hardware reset (CPU_PORn) and the execution of the first instruction of user code (typically this is the reset vector of U-Boot boot loader). | ||
| − | <section end=Body/> | + | == References == |
| + | [1] NXP, i.MX 93 Applications Processor Reference Manual | ||
| + | |||
| + | <section end="Body" /> | ||
[[Category:AURA]] | [[Category:AURA]] | ||
Latest revision as of 08:30, 15 February 2024
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| History | |||
|---|---|---|---|
| Issue Date | Notes | ||
| 2024/02/14 | First documentation release | ||
This page illustrates the characteristics of the AURA's boot subsystem. Reading of the chapter System Boot of the i.MX 93 Applications Processor Reference Manual is highly recommended [1], though. i.MX93 SOC features several options in terms of booting. Such options are detailed in that document.
It is worth remembering that, by default, AURA supports Single Boot modes (i.e. the Cortex-A55 is the boot core) as detailed in the rest of the document. Other options are available on-demand, however, allowing to implement different configurations. DAVE Embedded Systems' team is available for additional information on this matter. If necessary, please contact sales@dave.eu.
Contents
System boot[edit | edit source]
The boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM Cortex-A55 core to begin execution starting from the on-chip boot ROM. The boot ROM:
- determines whether the boot is secure or non-secure
- performs some initialization of the system and clean-ups
- reads the mode pins to determine the primary boot device
- once it is satisfied, it executes the boot code
Boot options[edit | edit source]
The default primary boot device is defined at the factory and identified by the 'Boot Mode' field of the ordering code as follows:
- 0: SPI NOR / SD option (SOM code: DAUxxx0xxxxR)
- 1: eMMC / SD option (SOM code: DAUxxx1xxxxR)
- 2: SPI NAND / SD option (SOM code: DAUxxx2xxxxR)
For both options an alternative primary boot from SD/MMC card is provided, selectable by driving low the BOOT_MODE_SEL signal. Bootable SD/MMC card connects via the SD2 (USDHC2) bus.
All boot modes provide 'single boot' mode, meaning that the Cortex-A55 is the first core to boot. In any case, boot process is managed by on-chip boot ROM code that is described in detail in processor's Reference Manual.
| Ordering code 'Boot Mode' fileld | BOOT_MODE_SEL | Primary boot device |
|---|---|---|
| 0 | 0 | SD/MMC card on USDHC2 |
| 1 | FlexSPI NOR on FLEXSPI1 | |
| 1 | 0 | SD/MMC card on USDHC2 |
| 1 | eMMC on USDHC1 | |
| 2 | 0 | SD/MMC card on USDHC2 |
| 1 | FlexSPI NAND on FLEXSPI1 |
Note on boot signals[edit | edit source]
- BOOT_MODE_SEL is latched when processor reset CPU_PORn is released. Inside the SOM, BOOT_MODE_SEL is pulled-up with 10 kohm.
- The iMX93x SoC uses some GPIOs to read the boot configuration set on the SOM: for this reason the SOM's ports UART1_TXD, UART2_TXD, SAI1_TXFS and SAI1_TXD0 are floating (high impedance) while CPU_PORn signal is low.
Note on boot[edit | edit source]
In case no valid image is found in primary boot device, boot ROM shall enable USB serial download mode automatically on USB OTG1.
Important note for manufacture mode management[edit | edit source]
When the internal boot and recover boot (if enabled) failed, the boot goes to the SD/MMC manufacture mode before the serial download mode.
By default, the SD/MMC manufacture mode is enabled. DAVE Embedded Systems do not blow the fuse of the DISABLE_SDMMC_MFG in order to disable it.
Boot ROM detects SD/MMC card on USDHC2 port. If a card is inserted, ROM will try to boot from it. SD2_CD_B is used as card detect signal during bootrom's manufacture mode. This signal need to be kept high during bootstrap stage to prevent the intervention of bootrom's manufacture mode, if it's not desidered.
Bootstrap stage has to be intended as the time elapsing between the release of hardware reset (CPU_PORn) and the execution of the first instruction of user code (typically this is the reset vector of U-Boot boot loader).
References[edit | edit source]
[1] NXP, i.MX 93 Applications Processor Reference Manual
