Difference between revisions of "AURA SOM/AURA Hardware/Power and Reset/System boot"

From DAVE Developer's Wiki
Jump to: navigation, search
(Created page with "{{subst:System_boot | nome-som=AURA| kit-code=MX93}}")
 
 
(14 intermediate revisions by 3 users not shown)
Line 1: Line 1:
−
<section begin=History/>
+
<section begin="History" />
 
{| style="border-collapse:collapse; "
 
{| style="border-collapse:collapse; "
−
!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
+
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
 
|-  
 
|-  
−
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date
+
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
−
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes
+
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
 
|-
 
|-
−
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Year/Month/Day
+
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |2024/02/14
−
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBD
+
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First documentation release
 
|-
 
|-
 
|}
 
|}
−
<section end=History/>
 
−
__FORCETOC__
 
−
<section begin=Body/>
 
  
 +
This page illustrates the characteristics of the AURA's boot subsystem. Reading of the chapter ''System Boot'' of the ''i.MX 93 Applications Processor Reference Manual'' is highly recommended [1], though. i.MX93 SOC features several options in terms of booting. Such options are detailed in that document.
 +
 +
It is worth remembering that, by default, AURA supports ''Single Boot'' modes (i.e. the Cortex-A55 is the boot core) as detailed in the rest of the document. Other options are available on-demand, however, allowing to implement different configurations. DAVE Embedded Systems' team is available for additional information on this matter. If necessary, please contact [mailto:sales@dave.eu sales@dave.eu].<section end="History" />__FORCETOC__<section begin="Body" />
 
== System boot ==
 
== System boot ==
  
−
The boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM core to begin execution starting from the on-chip boot ROM. The boot ROM:
+
The boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM Cortex-A55 core to begin execution starting from the on-chip boot ROM. The boot ROM:
 
* determines whether the boot is secure or non-secure
 
* determines whether the boot is secure or non-secure
 
* performs some initialization of the system and clean-ups
 
* performs some initialization of the system and clean-ups
Line 22: Line 22:
 
* once it is satisfied, it executes the boot code
 
* once it is satisfied, it executes the boot code
  
 +
=== Boot options ===
  
 +
The default primary boot device is defined at the factory and identified by the 'Boot Mode' field of the ordering code as follows:
 +
* 0: SPI NOR / SD option (SOM code: DAUxxx0xxxxR)
 +
* 1: eMMC / SD option (SOM code: DAUxxx1xxxxR)
 +
* 2: SPI NAND / SD option (SOM code: DAUxxx2xxxxR)
 +
For both options an alternative primary boot from SD/MMC card is provided, selectable by driving low the BOOT_MODE_SEL signal. Bootable SD/MMC card connects via the SD2 (USDHC2) bus.
  
−
''TBD: le sezioni di seguito sono valide - come esempio per AXEL Lite - da rivedere per gli altri prodotti ''
+
All boot modes provide 'single boot' mode, meaning that the Cortex-A55 is the first core to boot. In any case, boot process is managed by on-chip boot ROM code that is described in detail in processor's Reference Manual.
 +
{| class="wikitable"
 +
!Ordering code 'Boot Mode' fileld
 +
!BOOT_MODE_SEL
 +
!Primary boot device
 +
|-
 +
| rowspan="2" |0
 +
|0
 +
|SD/MMC card on USDHC2
 +
|-
 +
|1
 +
|FlexSPI NOR on FLEXSPI1
 +
|-
 +
| rowspan="2" |1
 +
|0
 +
|SD/MMC card on USDHC2
 +
|-
 +
|1
 +
|eMMC on USDHC1
 +
|-
 +
| rowspan="2" |2
 +
|0
 +
|SD/MMC card on USDHC2
 +
|-
 +
|1
 +
|FlexSPI NAND on FLEXSPI1
 +
|}
  
 +
=== Note on boot signals ===
 +
* BOOT_MODE_SEL is latched when processor reset CPU_PORn is released. Inside the SOM, BOOT_MODE_SEL is pulled-up with 10 kohm.
 +
* The iMX93x SoC uses some GPIOs to read the boot configuration set on the SOM: for this reason the SOM's ports UART1_TXD, UART2_TXD, SAI1_TXFS and SAI1_TXD0 are floating (high impedance) while CPU_PORn signal is low.
 +
[[File:AURA-boot-opt.png | 800px]]
  
−
== Boot options ==
+
=== Note on boot ===
 +
In case no valid image is found in primary boot device, boot ROM shall enable USB serial download mode automatically on USB OTG1.
  
−
Two options are available related to system boot. They are identified by the Boot field of the ordering code as follows:
+
===Important note for ''manufacture mode'' management===
−
* 0: SPI NOR / SD option (SOM code: DXLxxxx0xxR)
+
When the internal boot and recover boot (if enabled) failed, the boot goes to the SD/MMC manufacture mode before the serial download mode.
−
* 1: NAND / SD option (SOM code: DXLxxxx1xxR)
 
−
For both options the selection of primary boot device is determined by the BOOT_MODE_SEL signal as described in the following sections. BOOT_MODE_SEL is latched when processor reset is released.
 
  
−
In any case, boot process is managed by on-chip boot ROM code that is described in detail in processor's Reference Manual.
+
By default, the SD/MMC manufacture mode is enabled. DAVE Embedded Systems do not blow the fuse of the DISABLE_SDMMC_MFG in order to disable it.
  
−
=== SPI NOR / SD option ===
+
Boot ROM detects SD/MMC card on USDHC2 port. If a card is inserted, ROM will try to boot from it. SD2_CD_B is used as card detect signal during bootrom's manufacture mode. This signal need to be kept high during bootstrap stage to prevent the intervention of bootrom's manufacture mode, if it's not desidered.
−
Selection of primary boot device is determined by the BOOT_MODE_SEL signal as follows:
 
−
* BOOT_MODE_SEL = 0
 
−
** primary boot device is SD1
 
−
* boot ROM will try to boot a valid image from the SD card first, and then from the SPI NOR. In case no valid image is found, boot ROM shall enable USB serial download mode automatically
 
−
* BOOT_MODE_SEL = 1 or floating
 
−
** primary boot device is SPI NOR flash connected to eCSPI1
 
−
** in case no valid image is found in NOR flash, boot ROM shall enable USB serial download mode automatically
 
  
−
=== NAND / SD option ===
+
Bootstrap stage has to be intended as the time elapsing between the release of hardware reset (CPU_PORn) and the execution of the first instruction of user code (typically this is the reset vector of U-Boot boot loader).
−
Selection of primary boot device is determined by the BOOT_MODE_SEL signal as follows:
 
−
* BOOT_MODE_SEL = 0
 
−
** primary boot device is SD1
 
−
** in case no valid image is found in SD card, boot ROM shall enable USB serial download mode automatically
 
−
* BOOT_MODE_SEL = 1 or floating
 
−
** primary boot device is NAND flash
 
−
** in case no valid image is found in NAND flash, boot ROM shall enable USB serial download mode automatically
 
  
−
===Important note for DualLite/Solo based products (''manufacture mode'' management)===
+
== References ==
−
When Dual Lite or Solo processor are used, GPIO_1 and GPIO_4 signals need to be kept high during bootstrap stage in order to prevent the intervention of bootrom's ''manufacture mode''. Bootstrap stage has to be intended as the time elapsing between the release of hardware reset (CPU_PORn) and the execution of the first instruction of user code (typically this is the reset vector of U-Boot boot loader). Please note that, in case GPIO_1 signal is used to implement [[Reset_scheme_(AxelLite)#Handling_CPU-initiated_software_reset|software reset circuit]], it is high during bootstrap stage by design.
+
[1] NXP, i.MX 93 Applications Processor Reference Manual
  
−
<section end=Body/>
+
<section end="Body" />
  
 
[[Category:AURA]]
 
[[Category:AURA]]

Latest revision as of 08:30, 15 February 2024

HOME SOMs SBCs ToloMEO Embedded Assistant Sale-tag.pngGET A QUOTE Customer-service.pngONLINE HELPDESK
Roadmap IoT Services ML/AI services Embedded Design Services
History
Issue Date Notes
2024/02/14 First documentation release

This page illustrates the characteristics of the AURA's boot subsystem. Reading of the chapter System Boot of the i.MX 93 Applications Processor Reference Manual is highly recommended [1], though. i.MX93 SOC features several options in terms of booting. Such options are detailed in that document.

It is worth remembering that, by default, AURA supports Single Boot modes (i.e. the Cortex-A55 is the boot core) as detailed in the rest of the document. Other options are available on-demand, however, allowing to implement different configurations. DAVE Embedded Systems' team is available for additional information on this matter. If necessary, please contact sales@dave.eu.

System boot[edit | edit source]

The boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM Cortex-A55 core to begin execution starting from the on-chip boot ROM. The boot ROM:

  • determines whether the boot is secure or non-secure
  • performs some initialization of the system and clean-ups
  • reads the mode pins to determine the primary boot device
  • once it is satisfied, it executes the boot code

Boot options[edit | edit source]

The default primary boot device is defined at the factory and identified by the 'Boot Mode' field of the ordering code as follows:

  • 0: SPI NOR / SD option (SOM code: DAUxxx0xxxxR)
  • 1: eMMC / SD option (SOM code: DAUxxx1xxxxR)
  • 2: SPI NAND / SD option (SOM code: DAUxxx2xxxxR)

For both options an alternative primary boot from SD/MMC card is provided, selectable by driving low the BOOT_MODE_SEL signal. Bootable SD/MMC card connects via the SD2 (USDHC2) bus.

All boot modes provide 'single boot' mode, meaning that the Cortex-A55 is the first core to boot. In any case, boot process is managed by on-chip boot ROM code that is described in detail in processor's Reference Manual.

Ordering code 'Boot Mode' fileld BOOT_MODE_SEL Primary boot device
0 0 SD/MMC card on USDHC2
1 FlexSPI NOR on FLEXSPI1
1 0 SD/MMC card on USDHC2
1 eMMC on USDHC1
2 0 SD/MMC card on USDHC2
1 FlexSPI NAND on FLEXSPI1

Note on boot signals[edit | edit source]

  • BOOT_MODE_SEL is latched when processor reset CPU_PORn is released. Inside the SOM, BOOT_MODE_SEL is pulled-up with 10 kohm.
  • The iMX93x SoC uses some GPIOs to read the boot configuration set on the SOM: for this reason the SOM's ports UART1_TXD, UART2_TXD, SAI1_TXFS and SAI1_TXD0 are floating (high impedance) while CPU_PORn signal is low.

AURA-boot-opt.png

Note on boot[edit | edit source]

In case no valid image is found in primary boot device, boot ROM shall enable USB serial download mode automatically on USB OTG1.

Important note for manufacture mode management[edit | edit source]

When the internal boot and recover boot (if enabled) failed, the boot goes to the SD/MMC manufacture mode before the serial download mode.

By default, the SD/MMC manufacture mode is enabled. DAVE Embedded Systems do not blow the fuse of the DISABLE_SDMMC_MFG in order to disable it.

Boot ROM detects SD/MMC card on USDHC2 port. If a card is inserted, ROM will try to boot from it. SD2_CD_B is used as card detect signal during bootrom's manufacture mode. This signal need to be kept high during bootstrap stage to prevent the intervention of bootrom's manufacture mode, if it's not desidered.

Bootstrap stage has to be intended as the time elapsing between the release of hardware reset (CPU_PORn) and the execution of the first instruction of user code (typically this is the reset vector of U-Boot boot loader).

References[edit | edit source]

[1] NXP, i.MX 93 Applications Processor Reference Manual


HOME SOMs SBCs ToloMEO Embedded Assistant Sale-tag.pngGET A QUOTE Customer-service.pngONLINE HELPDESK
Roadmap IoT Services ML/AI services Embedded Design Services
Retrieved from "https://wiki.dave.eu/index.php?title=AURA_SOM/AURA_Hardware/Power_and_Reset/System_boot&oldid=20230"