Difference between revisions of "AURA SOM/AURA Hardware/Pinout Table"

From DAVE Developer's Wiki
Jump to: navigation, search
(Voltage domains)
(Pinout Table ODD pins declaration)
Line 332: Line 332:
 
| rowspan="8" |CPU.GPIO_IO06
 
| rowspan="8" |CPU.GPIO_IO06
 
| rowspan="8" |L20
 
| rowspan="8" |L20
| rowspan="8" |NVCC_GPIO
+
| rowspan="8" |NVCC_3V3
 
| rowspan="8" |IO
 
| rowspan="8" |IO
 
| rowspan="8" |
 
| rowspan="8" |
Line 363: Line 363:
 
| rowspan="8" |CPU.GPIO_IO18
 
| rowspan="8" |CPU.GPIO_IO18
 
| rowspan="8" |R18
 
| rowspan="8" |R18
| rowspan="8" |NVCC_GPIO
+
| rowspan="8" |NVCC_3V3
 
| rowspan="8" |IO
 
| rowspan="8" |IO
 
| rowspan="8" |
 
| rowspan="8" |
Line 394: Line 394:
 
| rowspan="8" |CPU.GPIO_IO09
 
| rowspan="8" |CPU.GPIO_IO09
 
| rowspan="8" |M21
 
| rowspan="8" |M21
| rowspan="8" |NVCC_GPIO
+
| rowspan="8" |NVCC_3V3
 
| rowspan="8" |IO
 
| rowspan="8" |IO
 
| rowspan="8" |
 
| rowspan="8" |
Line 425: Line 425:
 
| rowspan="8" |CPU.GPIO_IO08
 
| rowspan="8" |CPU.GPIO_IO08
 
| rowspan="8" |M20
 
| rowspan="8" |M20
| rowspan="8" |NVCC_GPIO
+
| rowspan="8" |NVCC_3V3
 
| rowspan="8" |IO
 
| rowspan="8" |IO
 
| rowspan="8" |
 
| rowspan="8" |
Line 491: Line 491:
 
| rowspan="8" |CPU.GPIO_IO10
 
| rowspan="8" |CPU.GPIO_IO10
 
| rowspan="8" |N17
 
| rowspan="8" |N17
| rowspan="8" |NVCC_GPIO
+
| rowspan="8" |NVCC_3V3
 
| rowspan="8" |IO
 
| rowspan="8" |IO
 
| rowspan="8" |
 
| rowspan="8" |
Line 532: Line 532:
 
| rowspan="8" |CPU.GPIO_IO11
 
| rowspan="8" |CPU.GPIO_IO11
 
| rowspan="8" |N18
 
| rowspan="8" |N18
| rowspan="8" |NVCC_GPIO
+
| rowspan="8" |NVCC_3V3
 
| rowspan="8" |IO
 
| rowspan="8" |IO
 
| rowspan="8" |
 
| rowspan="8" |
Line 563: Line 563:
 
| rowspan="4" |CPU.GPIO_IO11
 
| rowspan="4" |CPU.GPIO_IO11
 
| rowspan="4" |T16
 
| rowspan="4" |T16
| rowspan="4" |NVCC_GPIO
+
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |IO
 
| rowspan="4" |IO
 
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
 
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
Line 582: Line 582:
 
| rowspan="4" |CPU.GPIO_IO11
 
| rowspan="4" |CPU.GPIO_IO11
 
| rowspan="4" |V14
 
| rowspan="4" |V14
| rowspan="4" |NVCC_GPIO
+
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |IO
 
| rowspan="4" |IO
 
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
 
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
Line 601: Line 601:
 
| rowspan="4" |CPU.GPIO_IO12
 
| rowspan="4" |CPU.GPIO_IO12
 
| rowspan="4" |U14
 
| rowspan="4" |U14
| rowspan="4" |NVCC_GPIO
+
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |IO
 
| rowspan="4" |IO
 
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
 
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
Line 620: Line 620:
 
| rowspan="4" |CPU.GPIO_IO13
 
| rowspan="4" |CPU.GPIO_IO13
 
| rowspan="4" |T14
 
| rowspan="4" |T14
| rowspan="4" |NVCC_GPIO
+
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |IO
 
| rowspan="4" |IO
 
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
 
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
Line 639: Line 639:
 
| rowspan="4" |CPU.GPIO_IO21
 
| rowspan="4" |CPU.GPIO_IO21
 
| rowspan="4" |U16
 
| rowspan="4" |U16
| rowspan="4" |NVCC_GPIO
+
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |IO
 
| rowspan="4" |IO
 
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
 
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
Line 658: Line 658:
 
| rowspan="4" |CPU.GPIO_IO20
 
| rowspan="4" |CPU.GPIO_IO20
 
| rowspan="4" |V16
 
| rowspan="4" |V16
| rowspan="4" |NVCC_GPIO
+
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |IO
 
| rowspan="4" |IO
 
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
 
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
Line 687: Line 687:
 
| rowspan="5" |CPU.SD2_DATA0
 
| rowspan="5" |CPU.SD2_DATA0
 
| rowspan="5" |Y18
 
| rowspan="5" |Y18
| rowspan="5" |NVCC_GPIO
+
| rowspan="5" |NVCC_3V3
 
| rowspan="5" |IO
 
| rowspan="5" |IO
 
| rowspan="5" |
 
| rowspan="5" |
Line 709: Line 709:
 
| rowspan="5" |CPU.SD2_DATA1
 
| rowspan="5" |CPU.SD2_DATA1
 
| rowspan="5" |AA18
 
| rowspan="5" |AA18
| rowspan="5" |NVCC_GPIO
+
| rowspan="5" |NVCC_3V3
 
| rowspan="5" |IO
 
| rowspan="5" |IO
 
| rowspan="5" |
 
| rowspan="5" |
Line 731: Line 731:
 
| rowspan="5" |CPU.SD2_DATA2
 
| rowspan="5" |CPU.SD2_DATA2
 
| rowspan="5" |Y20
 
| rowspan="5" |Y20
| rowspan="5" |NVCC_GPIO
+
| rowspan="5" |NVCC_3V3
 
| rowspan="5" |IO
 
| rowspan="5" |IO
 
| rowspan="5" |
 
| rowspan="5" |
Line 753: Line 753:
 
| rowspan="5" |CPU.SD2_DATA3
 
| rowspan="5" |CPU.SD2_DATA3
 
| rowspan="5" |AA20
 
| rowspan="5" |AA20
| rowspan="5" |NVCC_GPIO
+
| rowspan="5" |NVCC_3V3
 
| rowspan="5" |IO
 
| rowspan="5" |IO
 
| rowspan="5" |
 
| rowspan="5" |
Line 775: Line 775:
 
| rowspan="6" |CPU.SD2_CMD
 
| rowspan="6" |CPU.SD2_CMD
 
| rowspan="6" |Y19
 
| rowspan="6" |Y19
| rowspan="6" |NVCC_GPIO
+
| rowspan="6" |NVCC_3V3
 
| rowspan="6" |IO
 
| rowspan="6" |IO
 
| rowspan="6" |
 
| rowspan="6" |
Line 800: Line 800:
 
| rowspan="5" |CPU.SD2_CLK
 
| rowspan="5" |CPU.SD2_CLK
 
| rowspan="5" |AA19
 
| rowspan="5" |AA19
| rowspan="5" |NVCC_GPIO
+
| rowspan="5" |NVCC_3V3
 
| rowspan="5" |IO
 
| rowspan="5" |IO
 
| rowspan="5" |
 
| rowspan="5" |
Line 832: Line 832:
 
| rowspan="8" |CPU.GPIO_IO14
 
| rowspan="8" |CPU.GPIO_IO14
 
| rowspan="8" |P20
 
| rowspan="8" |P20
| rowspan="8" |NVCC_GPIO
+
| rowspan="8" |NVCC_3V3
 
| rowspan="8" |IO
 
| rowspan="8" |IO
 
| rowspan="8" |
 
| rowspan="8" |
Line 863: Line 863:
 
| rowspan="8" |CPU.GPIO_IO15
 
| rowspan="8" |CPU.GPIO_IO15
 
| rowspan="8" |P21
 
| rowspan="8" |P21
| rowspan="8" |NVCC_GPIO
+
| rowspan="8" |NVCC_3V3
 
| rowspan="8" |IO
 
| rowspan="8" |IO
 
| rowspan="8" |
 
| rowspan="8" |
Line 894: Line 894:
 
| rowspan="5" |CPU.UART2_TXD//BOOT1
 
| rowspan="5" |CPU.UART2_TXD//BOOT1
 
| rowspan="5" |F21
 
| rowspan="5" |F21
| rowspan="5" |NVCC_GPIO
+
| rowspan="5" |NVCC_3V3
 
| rowspan="5" |IO
 
| rowspan="5" |IO
 
| rowspan="5" |Used as default console for Cortex-M33
 
| rowspan="5" |Used as default console for Cortex-M33
Line 916: Line 916:
 
| rowspan="6" |CPU.UART2_RXD
 
| rowspan="6" |CPU.UART2_RXD
 
| rowspan="6" |F20
 
| rowspan="6" |F20
| rowspan="6" |NVCC_GPIO
+
| rowspan="6" |NVCC_3V3
 
| rowspan="6" |IO
 
| rowspan="6" |IO
 
| rowspan="6" |Used as default console for Cortex-M33
 
| rowspan="6" |Used as default console for Cortex-M33
Line 941: Line 941:
 
| rowspan="5" |CPU.SD2_VSELECT
 
| rowspan="5" |CPU.SD2_VSELECT
 
| rowspan="5" |V18
 
| rowspan="5" |V18
| rowspan="5" |NVCC_GPIO
+
| rowspan="5" |NVCC_3V3
 
| rowspan="5" |IO
 
| rowspan="5" |IO
 
| rowspan="5" |
 
| rowspan="5" |
Line 963: Line 963:
 
| rowspan="4" |CPU.SD2_RESET_B
 
| rowspan="4" |CPU.SD2_RESET_B
 
| rowspan="4" |AA17
 
| rowspan="4" |AA17
| rowspan="4" |NVCC_GPIO
+
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |IO
 
| rowspan="4" |IO
 
| rowspan="4" |
 
| rowspan="4" |
Line 982: Line 982:
 
| rowspan="5" |CPU.I2C1_SCL
 
| rowspan="5" |CPU.I2C1_SCL
 
| rowspan="5" |C20
 
| rowspan="5" |C20
| rowspan="5" |NVCC_GPIO
+
| rowspan="5" |NVCC_3V3
 
| rowspan="5" |IO
 
| rowspan="5" |IO
 
| rowspan="5" |
 
| rowspan="5" |
Line 1,004: Line 1,004:
 
| rowspan="5" |CPU.I2C1_SDA
 
| rowspan="5" |CPU.I2C1_SDA
 
| rowspan="5" |C21
 
| rowspan="5" |C21
| rowspan="5" |NVCC_GPIO
+
| rowspan="5" |NVCC_3V3
 
| rowspan="5" |IO
 
| rowspan="5" |IO
 
| rowspan="5" |
 
| rowspan="5" |
Line 1,026: Line 1,026:
 
| rowspan="6" |CPU.SAI1_TXD0//BOOT3
 
| rowspan="6" |CPU.SAI1_TXD0//BOOT3
 
| rowspan="6" |H21
 
| rowspan="6" |H21
| rowspan="6" |NVCC_GPIO
+
| rowspan="6" |NVCC_3V3
 
| rowspan="6" |IO
 
| rowspan="6" |IO
 
| rowspan="6" |
 
| rowspan="6" |
Line 1,051: Line 1,051:
 
| rowspan="6" |CPU.SAI1_TXC
 
| rowspan="6" |CPU.SAI1_TXC
 
| rowspan="6" |G20
 
| rowspan="6" |G20
| rowspan="6" |NVCC_GPIO
+
| rowspan="6" |NVCC_3V3
 
| rowspan="6" |IO
 
| rowspan="6" |IO
 
| rowspan="6" |
 
| rowspan="6" |
Line 1,086: Line 1,086:
 
| rowspan="1" |CPU.ADC_IN0
 
| rowspan="1" |CPU.ADC_IN0
 
| rowspan="1" |B19
 
| rowspan="1" |B19
| rowspan="1" |NVCC_GPIO
+
| rowspan="1" |NVCC_3V3
 
| rowspan="1" |IO
 
| rowspan="1" |IO
 
| rowspan="1" |
 
| rowspan="1" |
Line 1,096: Line 1,096:
 
| rowspan="1" |CPU.ADC_IN1
 
| rowspan="1" |CPU.ADC_IN1
 
| rowspan="1" |A20
 
| rowspan="1" |A20
| rowspan="1" |NVCC_GPIO
+
| rowspan="1" |NVCC_3V3
 
| rowspan="1" |IO
 
| rowspan="1" |IO
 
| rowspan="1" |
 
| rowspan="1" |
Line 1,106: Line 1,106:
 
| rowspan="1" |CPU.ADC_IN2
 
| rowspan="1" |CPU.ADC_IN2
 
| rowspan="1" |B20
 
| rowspan="1" |B20
| rowspan="1" |NVCC_GPIO
+
| rowspan="1" |NVCC_3V3
 
| rowspan="1" |IO
 
| rowspan="1" |IO
 
| rowspan="1" |
 
| rowspan="1" |
Line 1,116: Line 1,116:
 
| rowspan="1" |CPU.ADC_IN3
 
| rowspan="1" |CPU.ADC_IN3
 
| rowspan="1" |B21
 
| rowspan="1" |B21
| rowspan="1" |NVCC_GPIO
+
| rowspan="1" |NVCC_3V3
 
| rowspan="1" |IO
 
| rowspan="1" |IO
 
| rowspan="1" |
 
| rowspan="1" |
Line 1,166: Line 1,166:
 
| rowspan="5" |CPU.I2C2_SDA<br>PMIC.SDA
 
| rowspan="5" |CPU.I2C2_SDA<br>PMIC.SDA
 
| rowspan="5" |D21<br>42
 
| rowspan="5" |D21<br>42
| rowspan="5" |NVCC_GPIO
+
| rowspan="5" |NVCC_3V3
 
| rowspan="5" |IO
 
| rowspan="5" |IO
 
| rowspan="5" |
 
| rowspan="5" |
Line 1,188: Line 1,188:
 
| rowspan="7" |CPU.I2C2_SCL<br>PMIC.SCL
 
| rowspan="7" |CPU.I2C2_SCL<br>PMIC.SCL
 
| rowspan="7" |D20<br>41
 
| rowspan="7" |D20<br>41
| rowspan="7" |NVCC_GPIO
+
| rowspan="7" |NVCC_3V3
 
| rowspan="7" |IO
 
| rowspan="7" |IO
 
| rowspan="7" |
 
| rowspan="7" |
Line 1,446: Line 1,446:
 
| rowspan="5" |CPU.GPIO_IO08
 
| rowspan="5" |CPU.GPIO_IO08
 
| rowspan="5" |M20
 
| rowspan="5" |M20
| rowspan="5" |NVCC_GPIO
+
| rowspan="5" |NVCC_3V3
 
| rowspan="5" |IO
 
| rowspan="5" |IO
 
| rowspan="5" |
 
| rowspan="5" |
Line 1,468: Line 1,468:
 
| rowspan="8" |CPU.GPIO_IO00
 
| rowspan="8" |CPU.GPIO_IO00
 
| rowspan="8" |J21
 
| rowspan="8" |J21
| rowspan="8" |NVCC_GPIO
+
| rowspan="8" |NVCC_3V3
 
| rowspan="8" |IO
 
| rowspan="8" |IO
 
| rowspan="8" |
 
| rowspan="8" |
Line 1,499: Line 1,499:
 
| rowspan="8" |CPU.GPIO_IO03
 
| rowspan="8" |CPU.GPIO_IO03
 
| rowspan="8" |K21
 
| rowspan="8" |K21
| rowspan="8" |NVCC_GPIO
+
| rowspan="8" |NVCC_3V3
 
| rowspan="8" |IO
 
| rowspan="8" |IO
 
| rowspan="8" |
 
| rowspan="8" |
Line 1,530: Line 1,530:
 
| rowspan="8" |CPU.GPIO_IO01
 
| rowspan="8" |CPU.GPIO_IO01
 
| rowspan="8" |K21
 
| rowspan="8" |K21
| rowspan="8" |NVCC_GPIO
+
| rowspan="8" |NVCC_3V3
 
| rowspan="8" |IO
 
| rowspan="8" |IO
 
| rowspan="8" |
 
| rowspan="8" |
Line 1,571: Line 1,571:
 
| rowspan="5" |CPU.UART1_TXD//BOOT0
 
| rowspan="5" |CPU.UART1_TXD//BOOT0
 
| rowspan="5" |E21
 
| rowspan="5" |E21
| rowspan="5" |NVCC_GPIO
+
| rowspan="5" |NVCC_3V3
 
| rowspan="5" |IO
 
| rowspan="5" |IO
 
| rowspan="5" |Used as default Linux console (Cortex-A55)
 
| rowspan="5" |Used as default Linux console (Cortex-A55)
Line 1,593: Line 1,593:
 
| rowspan="5" |CPU.UART1_RXD
 
| rowspan="5" |CPU.UART1_RXD
 
| rowspan="5" |E20
 
| rowspan="5" |E20
| rowspan="5" |NVCC_GPIO
+
| rowspan="5" |NVCC_3V3
 
| rowspan="5" |IO
 
| rowspan="5" |IO
 
| rowspan="5" |Used as default Linux console (Cortex-A55)
 
| rowspan="5" |Used as default Linux console (Cortex-A55)
Line 1,615: Line 1,615:
 
| rowspan="8" |CPU.GPIO_IO12
 
| rowspan="8" |CPU.GPIO_IO12
 
| rowspan="8" |N20
 
| rowspan="8" |N20
| rowspan="8" |NVCC_GPIO
+
| rowspan="8" |NVCC_3V3
 
| rowspan="8" |IO
 
| rowspan="8" |IO
 
| rowspan="8" |
 
| rowspan="8" |
Line 1,646: Line 1,646:
 
| rowspan="8" |CPU.GPIO_IO13
 
| rowspan="8" |CPU.GPIO_IO13
 
| rowspan="8" |N21
 
| rowspan="8" |N21
| rowspan="8" |NVCC_GPIO
+
| rowspan="8" |NVCC_3V3
 
| rowspan="8" |IO
 
| rowspan="8" |IO
 
| rowspan="8" |
 
| rowspan="8" |
Line 1,677: Line 1,677:
 
| rowspan="8" |CPU.GPIO_IO02
 
| rowspan="8" |CPU.GPIO_IO02
 
| rowspan="8" |K21
 
| rowspan="8" |K21
| rowspan="8" |NVCC_GPIO
+
| rowspan="8" |NVCC_3V3
 
| rowspan="8" |IO
 
| rowspan="8" |IO
 
| rowspan="8" |
 
| rowspan="8" |
Line 1,718: Line 1,718:
 
| rowspan="7" |CPU.PDM_BIT_STREAM0
 
| rowspan="7" |CPU.PDM_BIT_STREAM0
 
| rowspan="7" |J17
 
| rowspan="7" |J17
| rowspan="7" |NVCC_GPIO
+
| rowspan="7" |NVCC_3V3
 
| rowspan="7" |IO
 
| rowspan="7" |IO
 
| rowspan="7" |
 
| rowspan="7" |
Line 1,746: Line 1,746:
 
| rowspan="5" |CPU.PDM_CLK
 
| rowspan="5" |CPU.PDM_CLK
 
| rowspan="5" |G17
 
| rowspan="5" |G17
| rowspan="5" |NVCC_GPIO
+
| rowspan="5" |NVCC_3V3
 
| rowspan="5" |IO
 
| rowspan="5" |IO
 
| rowspan="5" |
 
| rowspan="5" |

Revision as of 15:47, 17 May 2023

History
ID# Issue Date Notes

17891

15/05/2023 Preliminary version


Connectors and Pinout Table[edit | edit source]

Connectors description[edit | edit source]

In the following table are described all available connectors integrated on AURA SOM:

Connector name Connector Type Notes Carrier board counterpart
J1 SODIMM DDR3 edge connector 204 pin TE Connectivity 2013289-1

The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to AURA pinout specifications. See the images below for reference:

AURA TOP view
AURA BOTTOM view

Pinout table naming conventions[edit | edit source]

This chapter contains the pinout description of the AURA module, grouped in two tables (odd and even pins) that report the pin mapping of the 204-pin SO-DIMM AURA connector.

Each row in the pinout tables contains the following information:

Pin Reference to the connector pin
Pin Name Pin (signal) name on the AURA connectors
Internal
connections
Connections to the AURA components
  • CPU.<x> : pin connected to CPU pad named <x>
  • CAN.<x> : pin connected to the CAN transceiver (TI SN65HVD232)
  • PMIC.<x> : pin connected to the Power Manager IC (NXP PCA9451A)
  • LAN.<x> : pin connected to the LAN PHY (Microchip LAN8830T-V)
Ball/pin # Component ball/pin number connected to signal
Voltage I/O voltage levels
Type Pin type:
  • I = Input
  • O = Output
  • D = Differential
  • Z = High impedance
  • S = Power supply voltage
  • G = Ground
  • A = Analog signal
Notes Remarks on special pin characteristics
Pin MUX alternative functions Muxes:
  • Pin ALT-0
  • ...
  • Pin ALT-N

The number of functions depends on platform

Voltage domains[edit | edit source]

Voltage domain Nominal voltage [V] Notes
3.3VIN 3.3 See Operational_characteristics of the SoM wiki page
NVCC_3V3 3.3 Voltage generated by the internal PSU. See Power Supply Unit (PSU) wiki page
VDD_ANA_1V8 1.8

Pinout Table ODD pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage

domain

Type Notes Alternative Functions
J1.1 DGND DGND - - G
J1.3 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.5 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.7 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.9 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.11 DGND DGND - - G
J1.13 ETH1_LED1 LAN.LED1/GPIO0 18 NVCC_3V3 O
J1.15 ETH1_LED2 LAN.LED2/GPIO1 16 NVCC_3V3 O
J1.17 DGND DGND - - G
J1.19 ETH1_TXRX0_P LAN.TXRXP_A 2 NVCC_3V3 D
J1.21 ETH1_TXRX0_M LAN.TXRXM_A 3 NVCC_3V3 D
J1.23 ETH1_TXRX1_P LAN.TXRXP_B 5 NVCC_3V3 D
J1.25 ETH1_TXRX1_M LAN.TXRXM_B 6 NVCC_3V3 D
J1.27 ETH1_TXRX2_P LAN.TXRXP_C 7 NVCC_3V3 D
J1.29 ETH1_TXRX2_M LAN.TXRXM_C 8 NVCC_3V3 D
J1.31 ETH1_TXRX3_P LAN.TXRXP_D 10 NVCC_3V3 D
J1.33 ETH1_TXRX3_M LAN.TXRXM_D 11 NVCC_3V3 D
J1.35 DGND DGND - - G
J1.37 ETH1_LED3 LAN.LED3/GPIO2 15 NVCC_3V3 O
J1.39 ETH1_LED4 LAN.LED4/GPIO3 14 NVCC_3V3 O
J1.41 ETH_OSC_EN 46 NVCC_3V3 I mounting option
J1.43 GPIO_IO06 CPU.GPIO_IO06 L20 NVCC_3V3 IO Pin ALT-0 GPIO2_IO06
Pin ALT-1 TMP5.CH0
Pin ALT-2 PDM.BIT_STREAM[1]
Pin ALT-3 LCDIF.D[2]
Pin ALT-4 SPI7.SOUT
Pin ALT-5 UART6.CTS_B
Pin ALT-6 I2C7.SDA
Pin ALT-7 FLEXIO1.FLEXIO[6]
J1.45 GPIO_IO18 CPU.GPIO_IO18 R18 NVCC_3V3 IO Pin ALT-0 GPIO2_IO18
Pin ALT-1 SAI3.RX_BCLK
Pin ALT-2 ISI.D[9]
Pin ALT-3 LCDIF.D[14]
Pin ALT-4 SPI5.PCS0
Pin ALT-5 SPI4.PCS0
Pin ALT-6 TMP5.CH2
Pin ALT-7 FLEXIO1.FLEXIO[18]
J1.47 GPIO_IO09 CPU.GPIO_IO09 M21 NVCC_3V3 IO Pin ALT-0 GPIO2_IO09
Pin ALT-1 SPI3.SIN
Pin ALT-2 ISI.D[3]
Pin ALT-3 LCDIF.D[5]
Pin ALT-4 TMP3.EXTCLK
Pin ALT-5 UART7.RX
Pin ALT-6 I2C7.SCL
Pin ALT-7 FLEXIO1.FLEXIO[9]
J1.49 GPIO_IO08 CPU.GPIO_IO08 M20 NVCC_3V3 IO Pin ALT-0 GPIO2_IO08
Pin ALT-1 SPI3.SPCS0
Pin ALT-2 ISI.D[2]
Pin ALT-3 LCDIF.D[4]
Pin ALT-4 TMP6.CH0
Pin ALT-5 UART7.TX
Pin ALT-6 I2C7.SDA
Pin ALT-7 FLEXIO1.FLEXIO[8]
J1.51
J1.53 SAI1_TXFS CPU.SAI1_TXFS//BOOT2 G21 NVCC_AON IO Pin ALT-0 SAI1.TX_SYNC
Pin ALT-1 SAI1.TX_DATA[1]
Pin ALT-2 SPI1.PCS0
Pin ALT-3 UART2_DTR_B
Pin ALT-4 MQS1.LEFT
Pin ALT-5 GPIO1_IO11//BOOT_MODE[2]
J1.55 GPIO_IO10 CPU.GPIO_IO10 N17 NVCC_3V3 IO Pin ALT-0 GPIO2_IO10
Pin ALT-1 SPI3.SOUT
Pin ALT-2 ISI.D[4]
Pin ALT-3 LCDIF.D[6]
Pin ALT-4 TMP4.EXTCLK
Pin ALT-5 UART7.CTS_B
Pin ALT-6 I2C8.SDA
Pin ALT-7 FLEXIO1.FLEXIO[10]
J1.57 DGND DGND - - G
J1.59 GPIO_IO11 CPU.GPIO_IO11 N18 NVCC_3V3 IO Pin ALT-0 GPIO2_IO10
Pin ALT-1 SPI3.SCLK
Pin ALT-2 ISI.D[5]
Pin ALT-3 LCDIF.D[7]
Pin ALT-4 TMP5.EXTCLK
Pin ALT-5 UART7.RTS_B
Pin ALT-6 I2C8.SCL
Pin ALT-7 FLEXIO1.FLEXIO[11]
J1.61 SD3_DATA0 CPU.GPIO_IO11 T16 NVCC_3V3 IO Optionally connected to internal Flex SPI (NOR or NAND option) Pin ALT-0 USDHC3.DATA0
Pin ALT-1 FLEX_SPI.A_DATA[0]
Pin ALT-4 FLEXIO1.FLEXIO[22]
Pin ALT-5 GPIO3_IO22
J1.63 SD3_DATA1 CPU.GPIO_IO11 V14 NVCC_3V3 IO Optionally connected to internal Flex SPI (NOR or NAND option) Pin ALT-0 USDHC3.DATA1
Pin ALT-1 FLEX_SPI.A_DATA[1]
Pin ALT-4 FLEXIO1.FLEXIO[23]
Pin ALT-5 GPIO3_IO23
J1.65 SD3_DATA2 CPU.GPIO_IO12 U14 NVCC_3V3 IO Optionally connected to internal Flex SPI (NOR or NAND option) Pin ALT-0 USDHC3.DATA2
Pin ALT-1 FLEX_SPI.A_DATA[2]
Pin ALT-4 FLEXIO1.FLEXIO[24]
Pin ALT-5 GPIO3_IO24
J1.67 SD3_DATA3 CPU.GPIO_IO13 T14 NVCC_3V3 IO Optionally connected to internal Flex SPI (NOR or NAND option) Pin ALT-0 USDHC3.DATA3
Pin ALT-1 FLEX_SPI.A_DATA[3]
Pin ALT-4 FLEXIO1.FLEXIO[25]
Pin ALT-5 GPIO3_IO25
J1.69 SD3_CMD CPU.GPIO_IO21 U16 NVCC_3V3 IO Optionally connected to internal Flex SPI (NOR or NAND option) Pin ALT-0 USDHC3.CMD
Pin ALT-1 FLEX_SPI.A_SS0_B
Pin ALT-4 FLEXIO1.FLEXIO[21]
Pin ALT-5 GPIO3_IO21
J1.71 SD3_CLK CPU.GPIO_IO20 V16 NVCC_3V3 IO Optionally connected to internal Flex SPI (NOR or NAND option) Pin ALT-0 USDHC3.CLK
Pin ALT-1 FLEX_SPI.A_SCLK
Pin ALT-4 FLEXIO1.FLEXIO[20]
Pin ALT-5 GPIO3_IO20
J1.73 DGND DGND - - G
J1.75 SD2_DATA0 CPU.SD2_DATA0 Y18 NVCC_3V3 IO Pin ALT-0 USDHC2.DATA0
Pin ALT-1 ENET2.1588_EVENT0_OUT
Pin ALT-2 CAN2.TX
Pin ALT-4 FLEXIO1.FLEXIO[3]
Pin ALT-5 GPIO3_IO03
J1.77 SD2_DATA1 CPU.SD2_DATA1 AA18 NVCC_3V3 IO Pin ALT-0 USDHC2.DATA1
Pin ALT-1 ENET2.1588_EVENT1_IN
Pin ALT-2 CAN2.RX
Pin ALT-4 FLEXIO1.FLEXIO[4]
Pin ALT-5 GPIO3_IO04
J1.79 SD2_DATA2 CPU.SD2_DATA2 Y20 NVCC_3V3 IO Pin ALT-0 USDHC2.DATA2
Pin ALT-1 ENET2.1588_EVENT1_OUT
Pin ALT-2 MQS1.RIGHT
Pin ALT-4 FLEXIO1.FLEXIO[5]
Pin ALT-5 GPIO3_IO05
J1.81 SD2_DATA3 CPU.SD2_DATA3 AA20 NVCC_3V3 IO Pin ALT-0 USDHC2.DATA3
Pin ALT-1 LPTMR2.ALT1
Pin ALT-2 MQS1.LEFT
Pin ALT-4 FLEXIO1.FLEXIO[6]
Pin ALT-5 GPIO3_IO06
J1.83 SD2_CMD CPU.SD2_CMD Y19 NVCC_3V3 IO Pin ALT-0 USDHC2.CMD
Pin ALT-1 ENET2.1588_EVENT0_IN
Pin ALT-2 I3C2.PUR
Pin ALT-3 I3C2.PUR_B
Pin ALT-4 FLEXIO1.FLEXIO[2]
Pin ALT-5 GPIO3_IO02
J1.85 SD2_CLK CPU.SD2_CLK AA19 NVCC_3V3 IO Pin ALT-0 USDHC2.CLK
Pin ALT-1 ENET_QOS.1588_EVENT0_OUT
Pin ALT-2 I3C2.SDA
Pin ALT-4 FLEXIO1.FLEXIO[1]
Pin ALT-5 GPIO3_IO01
J1.87 DGND DGND - - G
J1.89 GPIO_IO14 CPU.GPIO_IO14 P20 NVCC_3V3 IO Pin ALT-0 GPIO2_IO14
Pin ALT-1 UART3.TX
Pin ALT-2 ISI.D[6]
Pin ALT-3 LCDIF.D[10]
Pin ALT-4 SPI8.SOUT
Pin ALT-5 UART8.CTS_B
Pin ALT-6 UART4.TX
Pin ALT-7 FLEXIO1.FLEXIO[14]
J1.91 GPIO_IO15 CPU.GPIO_IO15 P21 NVCC_3V3 IO Pin ALT-0 GPIO2_IO15
Pin ALT-1 UART3.RX
Pin ALT-2 ISI.D[7]
Pin ALT-3 LCDIF.D[11]
Pin ALT-4 SPI8.SCK
Pin ALT-5 UART8.RTS_B
Pin ALT-6 UART4.RX
Pin ALT-7 FLEXIO1.FLEXIO[15]
J1.93 UART2_TXD CPU.UART2_TXD//BOOT1 F21 NVCC_3V3 IO Used as default console for Cortex-M33 Pin ALT-0 UART2_TX
Pin ALT-1 UART1.RTS_B
Pin ALT-2 SPI2.SCK
Pin ALT-3 TMP1.CH3
Pin ALT-5 GPIO1_IO07//BOOT_MODE[1]
J1.95 UART2_RXD CPU.UART2_RXD F20 NVCC_3V3 IO Used as default console for Cortex-M33 Pin ALT-0 UART2_RX
Pin ALT-1 UART1.CTS_B
Pin ALT-2 SPI2.SOUT
Pin ALT-3 TMP1.CH2
Pin ALT-4 SAI1.MCLK
Pin ALT-5 GPIO1_IO06
J1.97 SD2_VSELECT CPU.SD2_VSELECT V18 NVCC_3V3 IO Pin ALT-0 USDHC2.VSELECT
Pin ALT-1 USHDC2.WP
Pin ALT-2 LPTMR2.ALT3
Pin ALT-4 FLEXIO1.FLEXIO[19]
Pin ALT-5 GPIO3_IO19
J1.99 SD2_RESET_B CPU.SD2_RESET_B AA17 NVCC_3V3 IO Pin ALT-0 USDHC2.RESET_B
Pin ALT-1 LPTMR2.ALT2
Pin ALT-4 FLEXIO1.FLEXIO[7]
Pin ALT-5 GPIO3_IO07
J1.101 I2C1_SCL CPU.I2C1_SCL C20 NVCC_3V3 IO Pin ALT-0 I2C1.SCL
Pin ALT-1 I3C1.SCL
Pin ALT-2 UART1.DCB_B
Pin ALT-3 TMP2.CH0
Pin ALT-5 GPIO1_IO00
J1.103 I2C1_SDA CPU.I2C1_SDA C21 NVCC_3V3 IO Pin ALT-0 I2C1.SDA
Pin ALT-1 I3C1.SDA
Pin ALT-2 UART1.RIN_B
Pin ALT-3 TMP2.CH1
Pin ALT-5 GPIO1_IO01
J1.105 SAI1_TXD0 CPU.SAI1_TXD0//BOOT3 H21 NVCC_3V3 IO Pin ALT-0 SAI1.TX_DATA[0]
Pin ALT-1 UART2.RTS_B
Pin ALT-2 SPI1.SCK
Pin ALT-3 UART1.DTR_B
Pin ALT-4 CAN1.TX
Pin ALT-5 GPIO1_IO13//BOOT_MODE[3]
J1.107 SAI1_TXC CPU.SAI1_TXC G20 NVCC_3V3 IO Pin ALT-0 SAI1.TX_BCLK
Pin ALT-1 UART2.CTS_B
Pin ALT-2 SPI1.SIN
Pin ALT-3 UART1.DSR_B
Pin ALT-4 CAN1.RX
Pin ALT-5 GPIO1_IO12
J1.109 DGND DGND - - G
J1.111 ADC_IN0 CPU.ADC_IN0 B19 NVCC_3V3 IO Pin ALT-0 ANAMIX.ADC_IN0
J1.113 ADC_IN1 CPU.ADC_IN1 A20 NVCC_3V3 IO Pin ALT-0 ANAMIX.ADC_IN1
J1.115 ADC_IN2 CPU.ADC_IN2 B20 NVCC_3V3 IO Pin ALT-0 ANAMIX.ADC_IN2
J1.117 ADC_IN3 CPU.ADC_IN3 B21 NVCC_3V3 IO Pin ALT-0 ANAMIX.ADC_IN3
J1.119 PMIC_SCLH PMIC.SCLH 25 -
J1.121 PMIC_SDAH PMIC.SDAH 24 -
J1.123 PMIC_SCLL PMIC.SCLL 27 -
J1.125 PMIC_SDAL PMIC.SDAL 26 -
J1.127 I2C2_SDA CPU.I2C2_SDA
PMIC.SDA
D21
42
NVCC_3V3 IO Pin ALT-0 I2C2.SDA
Pin ALT-3 UART2.RIN_B
Pin ALT-4 TMP2.CH3
Pin ALT-5 SAI1.RX_BCLK
Pin ALT-5 GPIO1_IO03
J1.129 I2C2_SCL CPU.I2C2_SCL
PMIC.SCL
D20
41
NVCC_3V3 IO Pin ALT-0 I2C2.SCL
Pin ALT-1 I3C1.PUR
Pin ALT-3 UART2.DCB_B
Pin ALT-4 TMP2.CH2
Pin ALT-5 SAI1.RX_SYNC
Pin ALT-5 GPIO1_IO02
Pin ALT-6 I3C1.PUR_B
J1.131 DGND DGND - - G
J1.133 LVDS_CLK_N CPU.LVDS_CLK_N A3 VDD_ANA_1V8 D
J1.135 LVDS_CLK_P CPU.LVDS_CLK_P B3 VDD_ANA_1V8 D
J1.137 LVDS_TX0_N CPU.LVDS_TX0_N A5 VDD_ANA_1V8 D
J1.139 LVDS_TX0_P CPU.LVDS_TX0_P B5 VDD_ANA_1V8 D
J1.141 LVDS_TX1_N CPU.LVDS_TX1_N A4 VDD_ANA_1V8 D
J1.143 LVDS_TX1_P CPU.LVDS_TX1_P B4 VDD_ANA_1V8 D
J1.145 LVDS_TX2_N CPU.LVDS_TX2_N A2 VDD_ANA_1V8 D
J1.147 LVDS_TX2_P CPU.LVDS_TX2_P B2 VDD_ANA_1V8 D
J1.149 LVDS_TX3_N CPU.LVDS_TX3_N B1 VDD_ANA_1V8 D
J1.151 LVDS_TX3_P CPU.LVDS_TX3_P C1 VDD_ANA_1V8 D
J1.153 DGND DGND - - G
J1.155 DSI_CLK_N CPU.DSI_CLK_N D6 VDD_ANA_1V8 D
J1.157 DSI_CLK_P CPU.DSI_CLK_P E6 VDD_ANA_1V8 D
J1.159 DSI_TX0_N CPU.DSI_TX0_N A6 VDD_ANA_1V8 D
J1.161 DSI_TX0_P CPU.DSI_TX0_P B6 VDD_ANA_1V8 D
J1.163 DSI_TX1_N CPU.DSI_TX1_N A7 VDD_ANA_1V8 D
J1.165 DSI_TX1_P CPU.DSI_TX1_P B7 VDD_ANA_1V8 D
J1.167 DSI_TX2_N CPU.DSI_TX2_N A8 VDD_ANA_1V8 D
J1.169 DSI_TX2_P CPU.DSI_TX2_P B8 VDD_ANA_1V8 D
J1.171 DSI_TX3_N CPU.DSI_TX3_N A9 VDD_ANA_1V8 D
J1.173 DSI_TX3_P CPU.DSI_TX3_P B9 VDD_ANA_1V8 D
J1.175 DGND DGND - - G
J1.177 SD2_CD_B CPU.GPIO_IO08 M20 NVCC_3V3 IO Pin ALT-0 USDHC2.CD_B
Pin ALT-1 ENET_QOS.1588_EVENT0_IN
Pin ALT-2 I2C3.SCL
Pin ALT-4 FLEXIO1.FLEXIO[0]
Pin ALT-5 GPIO3_IO00
J1.179 GPIO_IO00 CPU.GPIO_IO00 J21 NVCC_3V3 IO Pin ALT-0 GPIO2_IO00
Pin ALT-1 I2C3.SDA
Pin ALT-2 ISI.PCLK
Pin ALT-3 LCDIF.PCLK
Pin ALT-4 SPI6.PCS0
Pin ALT-5 UART5.TX
Pin ALT-6 I2C5.SDA
Pin ALT-7 FLEXIO1.FLEXIO[0]
J1.181 GPIO_IO03 CPU.GPIO_IO03 K21 NVCC_3V3 IO Pin ALT-0 GPIO2_IO03
Pin ALT-1 I2C4.SCL
Pin ALT-2 ISI.LINE_VALID
Pin ALT-3 LCDIF.HSYNC
Pin ALT-4 SPI6.SCK
Pin ALT-5 UART5.RTS_B
Pin ALT-6 I2C6.SCL
Pin ALT-7 FLEXIO1.FLEXIO[3]
J1.183 GPIO_IO01 CPU.GPIO_IO01 K21 NVCC_3V3 IO Pin ALT-0 GPIO2_IO01
Pin ALT-1 I2C3.SCL
Pin ALT-2 ISI.D[0]
Pin ALT-3 LCDIF.DE
Pin ALT-4 SPI6.SIN
Pin ALT-5 UART5.RX
Pin ALT-6 I2C5.SCL
Pin ALT-7 FLEXIO1.FLEXIO[1]
J1.185 - - - -
J1.187 UART1_TXD CPU.UART1_TXD//BOOT0 E21 NVCC_3V3 IO Used as default Linux console (Cortex-A55) Pin ALT-0 UART1_TX
Pin ALT-1 SECO.TX
Pin ALT-2 SPI2.PCS0
Pin ALT-3 TPM1.CH1
Pin ALT-5 GPIO1_IO05//BOOT_MODE[0]
J1.189 UART1_RXD CPU.UART1_RXD E20 NVCC_3V3 IO Used as default Linux console (Cortex-A55) Pin ALT-0 UART1_RX
Pin ALT-1 SECO.RX
Pin ALT-2 SPI2.SIN
Pin ALT-3 TPM1.CH0
Pin ALT-5 GPIO1_IO04
J1.191 GPIO_IO12 CPU.GPIO_IO12 N20 NVCC_3V3 IO Pin ALT-0 GPIO2_IO12
Pin ALT-1 TPM3.CH2
Pin ALT-2 PDM.BIT_STREAM[2]
Pin ALT-3 LCDIF.D[8]
Pin ALT-4 SPI8.PCS0
Pin ALT-5 UART8.TX
Pin ALT-6 I2C8.SDA
Pin ALT-7 SAI3.RX_SYNC
J1.193 GPIO_IO13 CPU.GPIO_IO13 N21 NVCC_3V3 IO Pin ALT-0 GPIO2_IO13
Pin ALT-1 TPM4.CH2
Pin ALT-2 PDM.BIT_STREAM[3]
Pin ALT-3 LCDIF.D[9]
Pin ALT-4 SPI8.SIN
Pin ALT-5 UART8.RX
Pin ALT-6 I2C8.SCL
Pin ALT-7 FLEXIO1.FLEXIO[13]
J1.195 GPIO_IO02 CPU.GPIO_IO02 K21 NVCC_3V3 IO Pin ALT-0 GPIO2_IO13
Pin ALT-1 I2C4.SDA
Pin ALT-2 ISI.FRAME_VALID
Pin ALT-3 LCDIF.VSYNC
Pin ALT-4 SPI6.SOUT
Pin ALT-5 UART5.CTS_B
Pin ALT-6 I2C6.SDA
Pin ALT-7 FLEXIO1.FLEXIO[2]
J1.197 - - - -
J1.199 PDM_BIT_STREAM0 CPU.PDM_BIT_STREAM0 J17 NVCC_3V3 IO Pin ALT-0 PDM.BIT_STREAM[0]
Pin ALT-1 MQS1.RIGHT
Pin ALT-2 SPI1.PCS1
Pin ALT-3 TPM1.EXTCLK
Pin ALT-4 LPTMR1.ALT2
Pin ALT-5 GPIO1.IO09
Pin ALT-6 CAN1.RX
J1.201 PDM_CLK CPU.PDM_CLK G17 NVCC_3V3 IO Pin ALT-0 PDM_CLK
Pin ALT-1 MQS1.LEFT
Pin ALT-4 LPTMR1.ALT1
Pin ALT-5 GPIO1.IO08
Pin ALT-6 CAN1.TX
J1.203 DGND DGND - - G

Pinout Table EVEN pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage

domain

Type Notes Alternative Functions
J1.2 DGND DGND - - G
J1.4 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.6 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.8 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.10 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.12 DGND DGND - - G
J1.14 SYS_NRST PMIC.PMIC_RST_B 8 I
J1.16 CPU_ON_OFF CPU.ON_OFF A19 NVCC_3V3 I
J1.18 SOM_PGOOD - - NVCC_3V3 O
J1.20 BOOT_MODE_SEL BOOT MODE SELECTION - NVCC_3V3 I internal pull-up to NVCC_3V3
J1.22 CPU_PORn CPU.POR_B

PMIC.POR_B

A16

9

NVCC_BBSM_1V8 I/O internal pull-up 100k to NVCC_BBSM_1V8
J1.24 PMIC_ON_REQ PMIC.PMIC_ON_REQ 39 NVCC_BBSM_1V8 I internal pull-up 100k to NVCC_BBSM_1V8
J1.26 PDM_BIT_STREAM1 CPU.PDM_BIT_STREAM1 JG18 NVCC_3V3 IO Pin ALT-0 PDM.BIT_STREAM[1]
Pin ALT-1 M33.NMI
Pin ALT-2 SPI2.PCS1
Pin ALT-3 TPM2.EXTCLK
Pin ALT-4 LPTMR1.ALT3
Pin ALT-5 GPIO1.IO10
J1.28 WDOG_ANY CPU.PDM_BIT_STREAM1 JG18 NVCC_3V3 IO Pin ALT-0 WDOG1.WDOG_ANY
Pin ALT-5 GPIO1.IO15
J1.30 DGND DGND - - G
J1.32 PMIC_STBY_REQ PMIC.PMIC_STBY_REQ 40 NVCC_BBSM_1V8 O
J1.34 GPIO_IO17 CPU.GPIO_IO17 R20 NVCC_3V3 IO Pin ALT-0 GPIO2_IO17
Pin ALT-1 SAI3.MCLK
Pin ALT-2 ISI.D[8]
Pin ALT-3 LCDIF.D[13]
Pin ALT-4 UART3.RTS_B
Pin ALT-5 SPI4.PCS1
Pin ALT-6 UART4.RTS_B
Pin ALT-7 FLEXIO1.FLEXIO[17]
J1.36 GPIO_IO21 CPU.GPIO_IO21 T21 NVCC_3V3 IO Pin ALT-0 GPIO2_IO21
Pin ALT-1 SAI3.TX_DATA[0]
Pin ALT-2 PDM.CLK
Pin ALT-3 LCDIF.D[17]
Pin ALT-4 SPI5.SCK
Pin ALT-5 SPI4.SCK
Pin ALT-6 TMP4.CH1
Pin ALT-7 SAI3.RX_BCLK
J1.38 GPIO_IO29 CPU.GPIO_IO29 Y21 NVCC_3V3 IO Pin ALT-0 GPIO2_IO29
Pin ALT-1 I2C3.SCL
Pin ALT-7 FLEXIO1.FLEXIO[29]
J1.40 GPIO_IO07 CPU.GPIO_IO07 L21 NVCC_3V3 IO Pin ALT-0 GPIO2_IO07
Pin ALT-1 SPI3.PCS1
Pin ALT-2 ISI.D[1]
Pin ALT-3 LCDIF.D[3]
Pin ALT-4 SPI7.SCK
Pin ALT-5 UART6.RTS_B
Pin ALT-6 I2C7.SCL
Pin ALT-7 FLEXIO1.FLEXIO[7]
J1.42 GPIO_IO25//CAN_H CPU.GPIO_IO25

CAN.CANH

V21

7

NVCC_3V3 IO optional CAN transceiver Pin ALT-0 GPIO2_IO25
Pin ALT-1 USDHC3.DATA1
Pin ALT-2 CAN2.TX
Pin ALT-3 LCDIF.D[21]
Pin ALT-4 TMP4.CH3
Pin ALT-5 DAP.TCLK_SWCLK
Pin ALT-6 SPI7.PCS1
Pin ALT-7 FLEXIO1.FLEXIO[25]
J1.44 GPIO_IO27//CAN_L CPU.GPIO_IO27

CAN.CANL

W21

6

NVCC_3V3 IO optional CAN transceiver Pin ALT-0 GPIO2_IO27
Pin ALT-1 USDHC3.DATA3
Pin ALT-2 CAN2.RX
Pin ALT-3 LCDIF.D[23]
Pin ALT-4 TMP6.CH3
Pin ALT-5 DAP.TMS_SWDIO
Pin ALT-6 SPI5.PCS1
Pin ALT-7 FLEXIO1.FLEXIO[27]
J1.46 GPIO_IO24 CPU.GPIO_IO24 U21 NVCC_3V3 IO Pin ALT-0 GPIO2_IO24
Pin ALT-1 USDHC3.DATA0
Pin ALT-3 LCDIF.D[20]
Pin ALT-4 TMP3.CH3
Pin ALT-5 DAP.TDO_TRACESWO
Pin ALT-6 SPI6.PSC1
Pin ALT-7 FLEXIO1.FLEXIO[24]
J1.48 GPIO_IO28 CPU.GPIO_IO28 W20 NVCC_3V3 IO Pin ALT-0 GPIO2_IO28
Pin ALT-1 I2C3.SDA
Pin ALT-7 FLEXIO1.FLEXIO[28]
J1.50 CCM_CLK01 CPU.CCM_CLK01 AA2 NVCC_3V3 IO Pin ALT-0 CCMSRCGPCMIX.CLK01
Pin ALT-4 FLEXIO1.FLEXIO[26]
Pin ALT-5 GPIO3_IO26
J1.52 CCM_CLK02 CPU.CCM_CLK02 Y3 NVCC_3V3 IO Pin ALT-0 CCMSRCGPCMIX.CLK02
Pin ALT-4 FLEXIO1.FLEXIO[27]
Pin ALT-5 GPIO3_IO27
J1.54 CCM_CLK03 CPU.CCM_CLK03 U4 NVCC_3V3 IO Pin ALT-0 CCMSRCGPCMIX.CLK01
Pin ALT-4 FLEXIO2.FLEXIO[28]
Pin ALT-5 GPIO4_IO28
J1.56 DGND DGND - - G
J1.58 ETH_RSTn LAN.RESETn 43 NVCC_3V3 I Hardware mounting option
J1.60 ETH_INTn LAN.INT_N 39 NVCC_3V3 O Hardware mounting option
J1.62 SAI1_RXD0 CPU.SAI1_RXD0 H20 NVCC_3V3 IO Pin ALT-0 SAI1.RX_DATA[0]
Pin ALT-1 SAI1.MCLK
Pin ALT-2 SPI1.SOUT
Pin ALT-3 UART2.DSR_B
Pin ALT-4 MQS1.RIGHT
Pin ALT-5 GPIO1.IO14
J1.64 CCM_CLK04 CPU.CCM_CLK04 V4 NVCC_3V3 IO Pin ALT-0 CCMSRCGPCMIX.CLK04
Pin ALT-4 FLEXIO2.FLEXIO[29]
Pin ALT-5 GPIO4_IO29
J1.66 GPIO_IO16 CPU.GPIO_IO16 R21 NVCC_3V3 IO Pin ALT-0 GPIO2_IO16
Pin ALT-1 SAI3.TX_BCLK
Pin ALT-2 PDM.BIT_STREAM[2]
Pin ALT-3 LCDIF.D[12]
Pin ALT-4 UART3.CTS_B
Pin ALT-5 SPI4.PCS2
Pin ALT-6 UART4.CTS_B
Pin ALT-7 FLEXIO1.FLEXIO[16]
J1.68 GPIO_IO19 CPU.GPIO_IO19 R17 NVCC_3V3 IO Pin ALT-0 GPIO2_IO19
Pin ALT-1 SAI3.RX_SYNC
Pin ALT-2 PDM.BIT_STREAM[3]
Pin ALT-3 LCDIF.D[15]
Pin ALT-4 SPI5.SIN
Pin ALT-5 SPI4.SIN
Pin ALT-6 TMP4.CH2
Pin ALT-7 SAI3.TX_DATA[0]
J1.70 GPIO_IO26 CPU.GPIO_IO26 V20 NVCC_3V3 IO Pin ALT-0 GPIO2_IO26
Pin ALT-1 USDHC3.DATA2
Pin ALT-2 PDM.BIT_STREAM[1]
Pin ALT-3 LCDIF.D[22]
Pin ALT-4 TMP3.CH3
Pin ALT-5 DAP-TDI
Pin ALT-6 SPI8.PCS1
Pin ALT-7 SAI3.TX_SYNC
J1.72 GPIO_IO20 CPU.GPIO_IO20 T20 NVCC_3V3 IO Pin ALT-0 GPIO2_IO20
Pin ALT-1 SAI3.RX_DATA[0]
Pin ALT-2 PDM.BIT_STREAM[0]
Pin ALT-3 LCDIF.D[16]
Pin ALT-4 SPI5.SOUT
Pin ALT-5 SPI4.SOUT
Pin ALT-6 TMP3.CH1
Pin ALT-7 FLEXIO1.FLEXIO[20]
J1.74 GPIO_IO22 CPU.GPIO_IO22 U18 NVCC_3V3 IO Pin ALT-0 GPIO2_IO22
Pin ALT-1 USDHC3.CLK
Pin ALT-2 SPDIF1.IN
Pin ALT-3 LCDIF.D[18]
Pin ALT-4 TMP5.CH1
Pin ALT-5 TMP6.EXTCLK
Pin ALT-6 I2C5.SDA
Pin ALT-7 FLEXIO1.FLEXIO[22]
J1.76 GPIO_IO23 CPU.GPIO_IO23 U20 NVCC_3V3 IO Pin ALT-0 GPIO2_IO23
Pin ALT-1 USDHC3.CMD
Pin ALT-2 SPDIF1.OUT
Pin ALT-3 LCDIF.D[19]
Pin ALT-4 TMP6.CH1
Pin ALT-6 I2C5.SCL
Pin ALT-7 FLEXIO1.FLEXIO[23]
J1.78 GPIO_IO05 CPU.GPIO_IO05 L18 NVCC_3V3 IO Pin ALT-0 GPIO2_IO05
Pin ALT-1 TMP4.CH0
Pin ALT-2 PDM.BIT_STREAM[0]
Pin ALT-3 LCDIF.D[1]
Pin ALT-4 SPI7.SIN
Pin ALT-5 UART6.RX
Pin ALT-6 I2C6.SCL
Pin ALT-7 FLEXIO1.FLEXIO[5]
J1.80 GPIO_IO04 CPU.GPIO_IO04 L17 NVCC_3V3 IO Pin ALT-0 GPIO2_IO04
Pin ALT-1 TMP3.CH0
Pin ALT-2 PDM.CLK
Pin ALT-3 LCDIF.D[0]
Pin ALT-4 SPI7.PCS0
Pin ALT-5 UART6.TX
Pin ALT-6 I2C6.SDA
Pin ALT-7 FLEXIO1.FLEXIO[4]
J1.82 DGND DGND - - G
J1.84 TAMPER0 CPU.TAMPER0 B16 NVCC_3V3 IO Pin ALT-0 BBSMMIX.TAMPER0
J1.86 TAMPER1 CPU.TAMPER1 F14 NVCC_3V3 IO Pin ALT-0 BBSMMIX.TAMPER1