Difference between revisions of "AURA SOM/AURA Hardware/Pinout Table"

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(→‎Pinout Table ODD pins declaration)
(→‎Pinout Table ODD pins declaration)
Line 469: Line 469:
 
|
 
|
 
|-
 
|-
−
|J1.53
+
| rowspan="7" |J1.53
−
|
+
| rowspan="7" |SAI1_TXFS
−
|
+
| rowspan="7" |CPU.SAI1_TXFS//BOOT2
−
|
+
| rowspan="7" |G21
−
|
+
| rowspan="7" |NVCC_AON
−
|
+
| rowspan="7" |IO
 +
| rowspan="7" |
 +
|Pin ALT-0
 +
|SAI1.TX_SYNC
 +
|-
 +
|Pin ALT-1
 +
|SAI1.TX_DATA[1]
 +
|-
 +
|Pin ALT-2
 +
|SPI1.PCS0
 +
|-
 +
|Pin ALT-3
 +
|UART2_DTR_B
 +
|-
 +
|Pin ALT-4
 +
|MQS1.LEFT
 +
|-
 +
|Pin ALT-5
 +
|GPIO1_IO11
 +
|-
 +
|Pin ALT-6
 +
|BOOT_MODE[2]
 +
|-
 +
| rowspan="8" |J1.55
 +
| rowspan="8" |GPIO_IO10
 +
| rowspan="8" |CPU.GPIO_IO10
 +
| rowspan="8" |N17
 +
| rowspan="8" |NVCC_GPIO
 +
| rowspan="8" |IO
 +
| rowspan="8" |
 +
|Pin ALT-0
 +
|GPIO2_IO10
 +
|-
 +
|Pin ALT-1
 +
|SPI3.SOUT
 +
|-
 +
|Pin ALT-2
 +
|ISI.D[4]
 +
|-
 +
|Pin ALT-3
 +
|LCDIF.D[6]
 +
|-
 +
|Pin ALT-4
 +
|TMP4.EXTCLK
 +
|-
 +
|Pin ALT-5
 +
|UART7.CTS_B
 +
|-
 +
|Pin ALT-6
 +
|I2C8.SDA
 +
|-
 +
|Pin ALT-7
 +
|FLEXIO1.FLEXIO[10]
 +
|-
 +
|J1.57
 +
|DGND
 +
|DGND
 +
| -
 +
| -
 +
|G
 
|
 
|
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.55
+
| rowspan="8" |J1.59
−
|GPIO_IO10
+
| rowspan="8" |GPIO_IO11
−
|CPU.GPIO_IO10
+
| rowspan="8" |CPU.GPIO_IO11
−
|
+
| rowspan="8" |N18
−
|NVCC_GPIO
+
| rowspan="8" |NVCC_GPIO
−
|IO
+
| rowspan="8" |IO
−
|
+
| rowspan="8" |
−
|
+
|Pin ALT-0
−
|
+
|GPIO2_IO10
 +
|-
 +
|Pin ALT-1
 +
|SPI3.SCLK
 +
|-
 +
|Pin ALT-2
 +
|ISI.D[5]
 +
|-
 +
|Pin ALT-3
 +
|LCDIF.D[7]
 +
|-
 +
|Pin ALT-4
 +
|TMP5.EXTCLK
 +
|-
 +
|Pin ALT-5
 +
|UART7.RTS_B
 +
|-
 +
|Pin ALT-6
 +
|I2C8.SCL
 +
|-
 +
|Pin ALT-7
 +
|FLEXIO1.FLEXIO[11]
 +
|-
 +
| rowspan="4" |J1.61
 +
| rowspan="4" |SD3_DATA0
 +
| rowspan="4" |CPU.GPIO_IO11
 +
| rowspan="4" |T16
 +
| rowspan="4" |NVCC_GPIO
 +
| rowspan="4" |IO
 +
| rowspan="4" |
 +
|Pin ALT-0
 +
|USDHC3.DATA0
 +
|-
 +
|Pin ALT-1
 +
|FLE_SPI.A_DATA[0]
 +
|-
 +
|Pin ALT-4
 +
|FLEXIO1.FLEXIO[22]
 +
|-
 +
|Pin ALT-5
 +
|GPIO3_IO22
 +
|-
 +
| rowspan="4" |J1.63
 +
| rowspan="4" |SD3_DATA1
 +
| rowspan="4" |CPU.GPIO_IO11
 +
| rowspan="4" |V14
 +
| rowspan="4" |NVCC_GPIO
 +
| rowspan="4" |IO
 +
| rowspan="4" |
 +
|Pin ALT-0
 +
|USDHC3.DATA1
 +
|-
 +
|Pin ALT-1
 +
|FLE_SPI.A_DATA[1]
 +
|-
 +
|Pin ALT-4
 +
|FLEXIO1.FLEXIO[23]
 +
|-
 +
|Pin ALT-5
 +
|GPIO3_IO23
 +
|-
 +
| rowspan="4" |J1.65
 +
| rowspan="4" |SD3_DATA2
 +
| rowspan="4" |CPU.GPIO_IO12
 +
| rowspan="4" |U14
 +
| rowspan="4" |NVCC_GPIO
 +
| rowspan="4" |IO
 +
| rowspan="4" |
 +
|Pin ALT-0
 +
|USDHC3.DATA2
 +
|-
 +
|Pin ALT-1
 +
|FLE_SPI.A_DATA[2]
 +
|-
 +
|Pin ALT-4
 +
|FLEXIO1.FLEXIO[24]
 +
|-
 +
|Pin ALT-5
 +
|GPIO3_IO24
 +
|-
 +
| rowspan="4" |J1.67
 +
| rowspan="4" |SD3_DATA3
 +
| rowspan="4" |CPU.GPIO_IO13
 +
| rowspan="4" |T14
 +
| rowspan="4" |NVCC_GPIO
 +
| rowspan="4" |IO
 +
| rowspan="4" |
 +
|Pin ALT-0
 +
|USDHC3.DATA3
 +
|-
 +
|Pin ALT-1
 +
|FLE_SPI.A_DATA[3]
 +
|-
 +
|Pin ALT-4
 +
|FLEXIO1.FLEXIO[25]
 +
|-
 +
|Pin ALT-5
 +
|GPIO3_IO25
 +
|-
 +
| rowspan="4" |J1.69
 +
| rowspan="4" |SD3_CMD
 +
| rowspan="4" |CPU.GPIO_IO21
 +
| rowspan="4" |U16
 +
| rowspan="4" |NVCC_GPIO
 +
| rowspan="4" |IO
 +
| rowspan="4" |
 +
|Pin ALT-0
 +
|USDHC3.CMD
 +
|-
 +
|Pin ALT-1
 +
|FLE_SPI.A_SS0_B
 +
|-
 +
|Pin ALT-4
 +
|FLEXIO1.FLEXIO[21]
 +
|-
 +
|Pin ALT-5
 +
|GPIO3_IO21
 +
|-
 +
| rowspan="4" |J1.71
 +
| rowspan="4" |SD3_CLK
 +
| rowspan="4" |CPU.GPIO_IO20
 +
| rowspan="4" |V16
 +
| rowspan="4" |NVCC_GPIO
 +
| rowspan="4" |IO
 +
| rowspan="4" |
 +
|Pin ALT-0
 +
|USDHC3.CLK
 +
|-
 +
|Pin ALT-1
 +
|FLE_SPI.A_SCLK
 +
|-
 +
|Pin ALT-4
 +
|FLEXIO1.FLEXIO[20]
 +
|-
 +
|Pin ALT-5
 +
|GPIO3_IO20
 
|-
 
|-
−
|J1.57
+
|J1.73
 
|DGND
 
|DGND
 
|DGND
 
|DGND
Line 499: Line 693:
 
|
 
|
 
|-
 
|-
−
|J1.59
+
| rowspan="5" |J1.75
−
|GPIO_IO11
+
| rowspan="5" |SD2_DATA0
−
|CPU.GPIO_IO11
+
| rowspan="5" |CPU.SD2_DATA0
−
|
+
| rowspan="5" |Y18
−
|NVCC_GPIO
+
| rowspan="5" |NVCC_GPIO
−
|IO
+
| rowspan="5" |IO
 +
| rowspan="5" |
 +
|Pin ALT-0
 +
|USDHC2.DATA0
 +
|-
 +
|Pin ALT-1
 +
|ENET2.1588_EVENT0_OUT
 +
|-
 +
|Pin ALT-2
 +
|CAN2.TX
 +
|-
 +
|Pin ALT-4
 +
|FLEXIO1.FLEXIO[3]
 +
|-
 +
|Pin ALT-5
 +
|GPIO3_IO03
 +
|-
 +
| rowspan="5" |J1.77
 +
| rowspan="5" |SD2_DATA1
 +
| rowspan="5" |CPU.SD2_DATA1
 +
| rowspan="5" |AA18
 +
| rowspan="5" |NVCC_GPIO
 +
| rowspan="5" |IO
 +
| rowspan="5" |
 +
|Pin ALT-0
 +
|USDHC2.DATA1
 +
|-
 +
|Pin ALT-1
 +
|ENET2.1588_EVENT1_IN
 +
|-
 +
|Pin ALT-2
 +
|CAN2.RX
 +
|-
 +
|Pin ALT-4
 +
|FLEXIO1.FLEXIO[4]
 +
|-
 +
|Pin ALT-5
 +
|GPIO3_IO04
 +
|-
 +
| rowspan="5" |J1.79
 +
| rowspan="5" |SD2_DATA2
 +
| rowspan="5" |CPU.SD2_DATA2
 +
| rowspan="5" |Y20
 +
| rowspan="5" |NVCC_GPIO
 +
| rowspan="5" |IO
 +
| rowspan="5" |
 +
|Pin ALT-0
 +
|USDHC2.DATA2
 +
|-
 +
|Pin ALT-1
 +
|ENET2.1588_EVENT1_OUT
 +
|-
 +
|Pin ALT-2
 +
|MQS1.RIGHT
 +
|-
 +
|Pin ALT-4
 +
|FLEXIO1.FLEXIO[5]
 +
|-
 +
|Pin ALT-5
 +
|GPIO3_IO05
 +
|-
 +
| rowspan="5" |J1.81
 +
| rowspan="5" |SD2_DATA3
 +
| rowspan="5" |CPU.SD2_DATA3
 +
| rowspan="5" |AA20
 +
| rowspan="5" |NVCC_GPIO
 +
| rowspan="5" |IO
 +
| rowspan="5" |
 +
|Pin ALT-0
 +
|USDHC2.DATA3
 +
|-
 +
|Pin ALT-1
 +
|LPTMR2.ALT1
 +
|-
 +
|Pin ALT-2
 +
|MQS1.LEFT
 +
|-
 +
|Pin ALT-4
 +
|FLEXIO1.FLEXIO[6]
 +
|-
 +
|Pin ALT-5
 +
|GPIO3_IO06
 +
|-
 +
| rowspan="6" |J1.83
 +
| rowspan="6" |SD2_CMD
 +
| rowspan="6" |CPU.SD2_CMD
 +
| rowspan="6" |Y19
 +
| rowspan="6" |NVCC_GPIO
 +
| rowspan="6" |IO
 +
| rowspan="6" |
 +
|Pin ALT-0
 +
|USDHC2.CMD
 +
|-
 +
|Pin ALT-1
 +
|ENET2.1588_EVENT0_IN
 +
|-
 +
|Pin ALT-2
 +
|I3C2.PUR
 +
|-
 +
|Pin ALT-3
 +
|I3C2.PUR_B
 +
|-
 +
|Pin ALT-4
 +
|FLEXIO1.FLEXIO[2]
 +
|-
 +
|Pin ALT-5
 +
|GPIO3_IO02
 +
|-
 +
| rowspan="5" |J1.85
 +
| rowspan="5" |SD2_CLK
 +
| rowspan="5" |CPU.SD2_CLK
 +
| rowspan="5" |AA19
 +
| rowspan="5" |NVCC_GPIO
 +
| rowspan="5" |IO
 +
| rowspan="5" |
 +
|Pin ALT-0
 +
|USDHC2.CLK
 +
|-
 +
|Pin ALT-1
 +
|ENET_QOS.1588_EVENT0_OUT
 +
|-
 +
|Pin ALT-2
 +
|I3C2.SDA
 +
|-
 +
|Pin ALT-4
 +
|FLEXIO1.FLEXIO[1]
 +
|-
 +
|Pin ALT-5
 +
|GPIO3_IO01
 +
|-
 +
|J1.87
 +
|DGND
 +
|DGND
 +
| -
 +
| -
 +
|G
 
|
 
|
 
|
 
|

Revision as of 19:58, 15 May 2023

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History
ID# Issue Date Notes

17891

15/05/2023 Preliminary version


Connectors and Pinout Table[edit | edit source]

Connectors description[edit | edit source]

In the following table are described all available connectors integrated on AURA SOM:

Connector name Connector Type Notes Carrier board counterpart
J1 SODIMM DDR3 edge connector 204 pin TE Connectivity 2013289-1

The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to AURA pinout specifications. See the images below for reference:

AURA TOP view
AURA BOTTOM view

Pinout table naming conventions[edit | edit source]

This chapter contains the pinout description of the AURA module, grouped in two tables (odd and even pins) that report the pin mapping of the 204-pin SO-DIMM AURA connector.

Each row in the pinout tables contains the following information:

Pin Reference to the connector pin
Pin Name Pin (signal) name on the AURA connectors
Internal
connections 		Connections to the AURA components
  • CPU.<x> : pin connected to CPU pad named <x>
  • CAN.<x> : pin connected to the CAN transceiver (TI SN65HVD232)
  • PMIC.<x> : pin connected to the Power Manager IC (NXP PCA9451A)
  • LAN.<x> : pin connected to the LAN PHY (Microchip LAN8830T-V)
  • NOR.<x>: pin connected to the flash NOR
  • SV.<x>: pin connected to voltage supervisor
  • MTR: pin connected to voltage monitors
Ball/pin # Component ball/pin number connected to signal
Voltage I/O voltage levels
Type Pin type:
  • I = Input
  • O = Output
  • D = Differential
  • Z = High impedance
  • S = Power supply voltage
  • G = Ground
  • A = Analog signal
Notes Remarks on special pin characteristics
Pin MUX alternative functions Muxes:
  • Pin ALT-0
  • ...
  • Pin ALT-N

The number of functions depends on platform

Voltage domains[edit | edit source]

Voltage domain Nominal voltage [V] Notes
3.3VIN 3.3 See Operational_characteristics of the SoM wiki page
NVCC_3V3 3.3 Voltage generated by the internal PSU. See Power Supply Unit (PSU) wiki page
NVCC_GPIO 3.3 Voltage generated by the internal PSU. See Power Supply Unit (PSU) wiki page
VDD_ANA_1V8 1.8

Pinout Table ODD pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage

domain

Type Notes Alternative Functions
J1.1 DGND DGND - - G
J1.3 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.5 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.7 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.9 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.11 DGND DGND - - G
J1.13 ETH1_LED1 LAN.LED1/GPIO0 18 NVCC_3V3 O
J1.15 ETH1_LED2 LAN.LED2/GPIO1 16 NVCC_3V3 O
J1.17 DGND DGND - - G
J1.19 ETH1_TXRX0_P LAN.TXRXP_A 2 NVCC_3V3 D
J1.21 ETH1_TXRX0_M LAN.TXRXM_A 3 NVCC_3V3 D
J1.23 ETH1_TXRX1_P LAN.TXRXP_B 5 NVCC_3V3 D
J1.25 ETH1_TXRX1_M LAN.TXRXM_B 6 NVCC_3V3 D
J1.27 ETH1_TXRX2_P LAN.TXRXP_C 7 NVCC_3V3 D
J1.29 ETH1_TXRX2_M LAN.TXRXM_C 8 NVCC_3V3 D
J1.31 ETH1_TXRX3_P LAN.TXRXP_D 10 NVCC_3V3 D
J1.33 ETH1_TXRX3_M LAN.TXRXM_D 11 NVCC_3V3 D
J1.35 DGND DGND - - G
J1.37 ETH1_LED3 LAN.LED3/GPIO2 15 NVCC_3V3 O
J1.39 ETH1_LED4 LAN.LED4/GPIO3 14 NVCC_3V3 O
J1.41 ETH_OSC_EN 46 NVCC_3V3 I (mounting option)
J1.43 GPIO_IO06 CPU.GPIO_IO06 L20 NVCC_GPIO IO Pin ALT-0 GPIO2_IO06
Pin ALT-1 TMP5.CH0
Pin ALT-2 PDM.BIT_STREAM[1]
Pin ALT-3 LCDIF.D[2]
Pin ALT-4 SPI7.SOUT
Pin ALT-5 UART6.CTS_B
Pin ALT-6 I2C7.SDA
Pin ALT-7 FLEXIO1.FLEXIO[6]
J1.45 GPIO_IO18 CPU.GPIO_IO18 R18 NVCC_GPIO IO Pin ALT-0 GPIO2_IO18
Pin ALT-1 SAI3.RX_BCLK
Pin ALT-2 ISI.D[9]
Pin ALT-3 LCDIF.D[14]
Pin ALT-4 SPI5.PCS0
Pin ALT-5 SPI4.PCS0
Pin ALT-6 TMP5.CH2
Pin ALT-7 FLEXIO1.FLEXIO[18]
J1.47 GPIO_IO09 CPU.GPIO_IO09 M21 NVCC_GPIO IO Pin ALT-0 GPIO2_IO09
Pin ALT-1 SPI3.SIN
Pin ALT-2 ISI.D[3]
Pin ALT-3 LCDIF.D[5]
Pin ALT-4 TMP3.EXTCLK
Pin ALT-5 UART7.RX
Pin ALT-6 I2C7.SCL
Pin ALT-7 FLEXIO1.FLEXIO[9]
J1.49 GPIO_IO08 CPU.GPIO_IO08 M20 NVCC_GPIO IO Pin ALT-0 GPIO2_IO08
Pin ALT-1 SPI3.SPCS0
Pin ALT-2 ISI.D[2]
Pin ALT-3 LCDIF.D[4]
Pin ALT-4 TMP6.CH0
Pin ALT-5 UART7.TX
Pin ALT-6 I2C7.SDA
Pin ALT-7 FLEXIO1.FLEXIO[8]
J1.51
J1.53 SAI1_TXFS CPU.SAI1_TXFS//BOOT2 G21 NVCC_AON IO Pin ALT-0 SAI1.TX_SYNC
Pin ALT-1 SAI1.TX_DATA[1]
Pin ALT-2 SPI1.PCS0
Pin ALT-3 UART2_DTR_B
Pin ALT-4 MQS1.LEFT
Pin ALT-5 GPIO1_IO11
Pin ALT-6 BOOT_MODE[2]
J1.55 GPIO_IO10 CPU.GPIO_IO10 N17 NVCC_GPIO IO Pin ALT-0 GPIO2_IO10
Pin ALT-1 SPI3.SOUT
Pin ALT-2 ISI.D[4]
Pin ALT-3 LCDIF.D[6]
Pin ALT-4 TMP4.EXTCLK
Pin ALT-5 UART7.CTS_B
Pin ALT-6 I2C8.SDA
Pin ALT-7 FLEXIO1.FLEXIO[10]
J1.57 DGND DGND - - G
J1.59 GPIO_IO11 CPU.GPIO_IO11 N18 NVCC_GPIO IO Pin ALT-0 GPIO2_IO10
Pin ALT-1 SPI3.SCLK
Pin ALT-2 ISI.D[5]
Pin ALT-3 LCDIF.D[7]
Pin ALT-4 TMP5.EXTCLK
Pin ALT-5 UART7.RTS_B
Pin ALT-6 I2C8.SCL
Pin ALT-7 FLEXIO1.FLEXIO[11]
J1.61 SD3_DATA0 CPU.GPIO_IO11 T16 NVCC_GPIO IO Pin ALT-0 USDHC3.DATA0
Pin ALT-1 FLE_SPI.A_DATA[0]
Pin ALT-4 FLEXIO1.FLEXIO[22]
Pin ALT-5 GPIO3_IO22
J1.63 SD3_DATA1 CPU.GPIO_IO11 V14 NVCC_GPIO IO Pin ALT-0 USDHC3.DATA1
Pin ALT-1 FLE_SPI.A_DATA[1]
Pin ALT-4 FLEXIO1.FLEXIO[23]
Pin ALT-5 GPIO3_IO23
J1.65 SD3_DATA2 CPU.GPIO_IO12 U14 NVCC_GPIO IO Pin ALT-0 USDHC3.DATA2
Pin ALT-1 FLE_SPI.A_DATA[2]
Pin ALT-4 FLEXIO1.FLEXIO[24]
Pin ALT-5 GPIO3_IO24
J1.67 SD3_DATA3 CPU.GPIO_IO13 T14 NVCC_GPIO IO Pin ALT-0 USDHC3.DATA3
Pin ALT-1 FLE_SPI.A_DATA[3]
Pin ALT-4 FLEXIO1.FLEXIO[25]
Pin ALT-5 GPIO3_IO25
J1.69 SD3_CMD CPU.GPIO_IO21 U16 NVCC_GPIO IO Pin ALT-0 USDHC3.CMD
Pin ALT-1 FLE_SPI.A_SS0_B
Pin ALT-4 FLEXIO1.FLEXIO[21]
Pin ALT-5 GPIO3_IO21
J1.71 SD3_CLK CPU.GPIO_IO20 V16 NVCC_GPIO IO Pin ALT-0 USDHC3.CLK
Pin ALT-1 FLE_SPI.A_SCLK
Pin ALT-4 FLEXIO1.FLEXIO[20]
Pin ALT-5 GPIO3_IO20
J1.73 DGND DGND - - G
J1.75 SD2_DATA0 CPU.SD2_DATA0 Y18 NVCC_GPIO IO Pin ALT-0 USDHC2.DATA0
Pin ALT-1 ENET2.1588_EVENT0_OUT
Pin ALT-2 CAN2.TX
Pin ALT-4 FLEXIO1.FLEXIO[3]
Pin ALT-5 GPIO3_IO03
J1.77 SD2_DATA1 CPU.SD2_DATA1 AA18 NVCC_GPIO IO Pin ALT-0 USDHC2.DATA1
Pin ALT-1 ENET2.1588_EVENT1_IN
Pin ALT-2 CAN2.RX
Pin ALT-4 FLEXIO1.FLEXIO[4]
Pin ALT-5 GPIO3_IO04
J1.79 SD2_DATA2 CPU.SD2_DATA2 Y20 NVCC_GPIO IO Pin ALT-0 USDHC2.DATA2
Pin ALT-1 ENET2.1588_EVENT1_OUT
Pin ALT-2 MQS1.RIGHT
Pin ALT-4 FLEXIO1.FLEXIO[5]
Pin ALT-5 GPIO3_IO05
J1.81 SD2_DATA3 CPU.SD2_DATA3 AA20 NVCC_GPIO IO Pin ALT-0 USDHC2.DATA3
Pin ALT-1 LPTMR2.ALT1
Pin ALT-2 MQS1.LEFT
Pin ALT-4 FLEXIO1.FLEXIO[6]
Pin ALT-5 GPIO3_IO06
J1.83 SD2_CMD CPU.SD2_CMD Y19 NVCC_GPIO IO Pin ALT-0 USDHC2.CMD
Pin ALT-1 ENET2.1588_EVENT0_IN
Pin ALT-2 I3C2.PUR
Pin ALT-3 I3C2.PUR_B
Pin ALT-4 FLEXIO1.FLEXIO[2]
Pin ALT-5 GPIO3_IO02
J1.85 SD2_CLK CPU.SD2_CLK AA19 NVCC_GPIO IO Pin ALT-0 USDHC2.CLK
Pin ALT-1 ENET_QOS.1588_EVENT0_OUT
Pin ALT-2 I3C2.SDA
Pin ALT-4 FLEXIO1.FLEXIO[1]
Pin ALT-5 GPIO3_IO01
J1.87 DGND DGND - - G
J1.131 DGND DGND - - G
J1.133 LVDS_CLK_N CPU.LVDS_CLK_N A3 VDD_ANA_1V8 D
J1.135 LVDS_CLK_P CPU.LVDS_CLK_P B3 VDD_ANA_1V8 D
J1.137 LVDS_TX0_N CPU.LVDS_TX0_N A5 VDD_ANA_1V8 D
J1.139 LVDS_TX0_P CPU.LVDS_TX0_P B5 VDD_ANA_1V8 D
J1.141 LVDS_TX1_N CPU.LVDS_TX1_N A4 VDD_ANA_1V8 D
J1.143 LVDS_TX1_P CPU.LVDS_TX1_P B4 VDD_ANA_1V8 D
J1.145 LVDS_TX2_N CPU.LVDS_TX2_N A2 VDD_ANA_1V8 D
J1.147 LVDS_TX2_P CPU.LVDS_TX2_P B2 VDD_ANA_1V8 D
J1.149 LVDS_TX3_N CPU.LVDS_TX3_N B1 VDD_ANA_1V8 D
J1.151 LVDS_TX3_P CPU.LVDS_TX3_P C1 VDD_ANA_1V8 D
J1.153 DGND DGND - - G
J1.155 DSI_CLK_N CPU.DSI_CLK_N D6 VDD_ANA_1V8 D
J1.157 DSI_CLK_P CPU.DSI_CLK_P E6 VDD_ANA_1V8 D
J1.159 DSI_TX0_N CPU.DSI_TX0_N A6 VDD_ANA_1V8 D
J1.161 DSI_TX0_P CPU.DSI_TX0_P B6 VDD_ANA_1V8 D
J1.163 DSI_TX1_N CPU.DSI_TX1_N A7 VDD_ANA_1V8 D
J1.165 DSI_TX1_P CPU.DSI_TX1_P B7 VDD_ANA_1V8 D
J1.167 DSI_TX2_N CPU.DSI_TX2_N A8 VDD_ANA_1V8 D
J1.169 DSI_TX2_P CPU.DSI_TX2_P B8 VDD_ANA_1V8 D
J1.171 DSI_TX3_N CPU.DSI_TX3_N A9 VDD_ANA_1V8 D
J1.173 DSI_TX3_P CPU.DSI_TX3_P B9 VDD_ANA_1V8 D
J1.175 DGND DGND - - G
J1.177 SD2_CD_B CPU.GPIO_IO08 M20 NVCC_GPIO IO Pin ALT-0 USDHC2.CD_B
Pin ALT-1 ENET_QOS.1588_EVENT0_IN
Pin ALT-2 I2C3.SCL
Pin ALT-4 FLEXIO1.FLEXIO[0]
Pin ALT-5 GPIO3_IO00

Pinout Table EVEN pins declaration[edit | edit source]

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