Difference between revisions of "AURA SOM/AURA Hardware/Peripherals/MIPI"
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==Peripheral MIPI == | ==Peripheral MIPI == | ||
| − | + | The AURA SOM based on i.MX93 SoC has two MIPI interfaces: | |
| − | + | ||
| + | * One 4-lane MIPI-DPHY DSI Tx PHY and MIPI-DSI Controller | ||
| + | * One 2-lane MIPI-DPHY CSI Rx PHY and MIPI-CSI Controller compliant to MIPI-DSI specification v1.2 and MIPI-DPHY specification v1.2 | ||
=== Description === | === Description === | ||
| − | The MIPI interface available | + | The MIPI-DSI controller supports the following features: |
| + | * Configurable selection of system interfaces: | ||
| + | ** AMBA APB for control and optional support for Generic and DCS commands | ||
| + | ** Display Pixel Interface (DPI) for Video mode interface (optional) | ||
| + | * Fault recovery mechanisms | ||
| + | * Ultra Low-Power mode with PLL disabled | ||
| + | * DPI features: | ||
| + | ** DPI signals programmable polarity | ||
| + | ** Extended resolutions beyond the DPI standard | ||
| + | ** Maximum resolution limited by available DSI physical link bandwidth, which is determined by the number of physical (up to 2048x1080@60Hz 24bpp with 4 lanes) | ||
| + | lanes and the maximum speed that they can achieve | ||
| + | * Video pattern generator | ||
| − | The MIPI | + | The MIPI CSI-2 controller receives data from a CSI-2 compliant camera sensor and supports the following blocks: |
| − | + | * PHY-Protocol Interface (PPI) Data Processor and Pattern Generator | |
| − | * | + | * De-scrambler |
| − | * | + | * PHY Adaptation Layer |
| − | * | + | * Image Pixel Interface (IPI) Controller (48-bit parallel bus operating at pixel clock rate) |
| − | * | + | ** Two operating modes: Camera Timing and Controller Timing |
| + | ** Generates pixel stream (48 or 16 bit modes) | ||
| + | ** data formats: YUV, RGB, RAW, User defined | ||
===Pin mapping=== | ===Pin mapping=== | ||
The Pin mapping is described in the [[AURA SOM/AURA Hardware/Pinout_Table | Pinout table section]] | The Pin mapping is described in the [[AURA SOM/AURA Hardware/Pinout_Table | Pinout table section]] | ||
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[[Category:AURA]] | [[Category:AURA]] | ||
Latest revision as of 09:09, 13 September 2023
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| 2023/09/13 | First release | ||
Peripheral MIPI[edit | edit source]
The AURA SOM based on i.MX93 SoC has two MIPI interfaces:
- One 4-lane MIPI-DPHY DSI Tx PHY and MIPI-DSI Controller
- One 2-lane MIPI-DPHY CSI Rx PHY and MIPI-CSI Controller compliant to MIPI-DSI specification v1.2 and MIPI-DPHY specification v1.2
Description[edit | edit source]
The MIPI-DSI controller supports the following features:
- Configurable selection of system interfaces:
- AMBA APB for control and optional support for Generic and DCS commands
- Display Pixel Interface (DPI) for Video mode interface (optional)
- Fault recovery mechanisms
- Ultra Low-Power mode with PLL disabled
- DPI features:
- DPI signals programmable polarity
- Extended resolutions beyond the DPI standard
- Maximum resolution limited by available DSI physical link bandwidth, which is determined by the number of physical (up to 2048x1080@60Hz 24bpp with 4 lanes)
lanes and the maximum speed that they can achieve
- Video pattern generator
The MIPI CSI-2 controller receives data from a CSI-2 compliant camera sensor and supports the following blocks:
- PHY-Protocol Interface (PPI) Data Processor and Pattern Generator
- De-scrambler
- PHY Adaptation Layer
- Image Pixel Interface (IPI) Controller (48-bit parallel bus operating at pixel clock rate)
- Two operating modes: Camera Timing and Controller Timing
- Generates pixel stream (48 or 16 bit modes)
- data formats: YUV, RGB, RAW, User defined
Pin mapping[edit | edit source]
The Pin mapping is described in the Pinout table section
