AURA SOM/AURA Evaluation Kit/Interfaces and Connectors/LVDS

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History
Issue Date Notes
2024/02/13 First documentation release



LVDS[edit | edit source]

Description[edit | edit source]

SBC AXEL provides two LVDS interfaces, LVDS0 and LVDS1. AURA SOM supports one LVDS channel on J8 Hirose (cod. DF13A-20DP-1.25V) double row 1.25mm pitch miniature crimping connector.


LVDS connectors

Signals[edit | edit source]

The following tables describes the interface signals

LVDS0[edit | edit source]

Pin# SOM Pin# Pin name Pin function Pin Notes
1, 2 - 3.3V_LCD0 3.3 V
3, 4, 7, 10,

13, 16, 19

- DGND Ground
5 J10.137 LVDS0_TX0_N LVDS Data 0 -
6 J10.139 LVDS0_TX0_P LVDS Data 0 +
8 J10.141 LVDS0_TX1_N LVDS Data 1 -
9 J10.143 LVDS0_TX1_P LVDS Data 1 +
11 J10.145 LVDS0_TX2_N LVDS Data 2 -
12 J10.147 LVDS0_TX2_P LVDS Data 2 +
14 J10.133 LVDS0_CLK_N LVDS Clock -
15 J10.135 LVDS0_CLK_P LVDS Clock +
17 J10.149 LVDS0_P17 LVDS Data 3 -
18 J10.151 LVDS0_P18 LVDS Data 3 +
20 J10.46 LVDS0_P20 TPM3.CH3

Device mapping[edit | edit source]

LVDS is mapped to LVDS-1 DRM "connector": see DESK-MX9-L LVDS peripheral.

Power sequence[edit | edit source]

Most of the LCD panels have many supplies and need a specific timing to power the rails and start the signals.

The Evaluation Kit provides GPIO controlled power rails that can be leveraged both at bootloader and kernel level to meet any specifications.

The following sections describe the available rails:

3V3_LCD[edit | edit source]

The most common voltage to supply the LCD panel internal rail 3V3_LCD0 is enabled by GPIO1_IO10

5V_LCD[edit | edit source]

The most common voltage to supply the LCD panel backlight rail 5V_LCD0 is enabled by GPIO2_IO24

Device usage[edit | edit source]

The associated framebuffer device is accessed in Linux through the standard graphic access.