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If a voltage drop occurs, voltage Voltage monitors can trigger a power resetIf a voltage drop occurs.
=== CPU_PORn ===
The following devices can assert this active-low signal:
* PMIC
* multiple-voltage monitor: this device monitors critical power voltages and triggers a reset pulse in case any of these exhibits a brownout condition
Since SPI NOR flash can be used as a boot device, CPU_PORn is connected to this device too. This guarantees it is in a known state when reset signal is released.
Ciclo di reset completo utilizzare
→Reset scheme and control signals
AURA SOM provides the following reset signals:
* '''SYS_nRST''', to performs a PMIC reset (cold or warm reset depends on PIMIC configuration register)* '''WDOG_B''', pulled-up with 100 kohmto performs a PMIC reset (cold or warm reset depends on PIMIC configuration register) * '''CPU_PORnPMIC_ON_REQ''', pulled-up with 100 kohm. This signalto start a PMIC power sequence, pilot by so that reboot the PMIC, reset SoC's CPU and onboard eMMC and ethernet PHY.* '''PMIC_INTnCPU_PORn''', pulled-up with 10 kohmto force memories and peripherals to reset, in order to bring them in a known condition
Furthermore, some control signals are avaible:
* '''SOM_PGOOD''', to turn on circuitry external to the SOM * '''PMIC_ON_REQPMIC_STBY_REQ''', pulled-down with 100 kohmto generate proper power for the SoC sleep mode* '''PMIC_STBY_REQONOFF''', pulled-down with 100 kohm* '''ONOFFPMIC_INTn''', pulled-up with 100 kohmto manage PMIC register interrupts
The electrical and functional characteristics of these signals are listed in the following table:
|Externally
|PMIC
|PMIC performs reset (cold or warm reset depends on its configuration register) when SYS_nRST is asserted low.
|-
|'''WDOG_B'''
|Externally or SoC
|PMIC
|PMIC performs reset (cold or warm reset depends on its configuration register) when WDOG_B is asserted low.
|-
|'''CPU_PORn'''
|PMIC
|SoC, onboard eMMC and PHY ETH, External
|Reset memories and peripherals internal and external to the SOM after a power-on sequence. This guarantees it is in a known state when reset signal is released.
|-
|'''SOM_PGOOD'''
|SOM
|External
|Turn on the external circuitry of the SOMwhen the SoC is ready, in order to prevent backpower.
|-
|'''PMIC_INTn'''
|PMIC
|SoC and External
|PMIC_INTn is asserted low when an interrupt bit status in PMIC's register is changed.
|-
|'''PMIC_ON_REQ'''
|PMIC starts power on sequence when PMIC_ON_REQ is asserted high.
|-
|'''PMIC_STBY_REQ'''
|SoC enters in power down when ONOFF is asserted high. The main power must remain active so that some data can be stored even if the processor is turned off. See Battery-Backed Non-Secure Module (BBNSM) on reference manual.
|}
=== Handling CPU-initiated software reset ===