dave_user
45
edits
Changes
m
→Reset scheme and control signals
|PMIC
|SoC, onboard eMMC and PHY ETH, External
|Reset peripherals internal and external to the SOM after a power-on sequence.
|-
|'''SOM_PGOOD'''
|Externally or SoC
|PMIC
|PMIC starts power on sequence when PMIC_ON_REQ is asserted high. If a voltage drop occurs, voltage monitors can trigger a power reset.
|-
|'''PMIC_STBY_REQ'''
|Externally or SoC
|PMIC
|PMIC enters in standby mode when PMIC_STBY_REQ is asserted high. This allows the SoC to enter sleep mode.
|-
|'''ONOFF'''
|Externally
|SoC
|SoC enters in power down when ONOFF is asserted high. The main power must remain active so that some data can be stored even if the processor is turned off. See Battery-Backed Non-Secure Module (BBNSM) on reference manual.
|}