Difference between revisions of "AXEL ULite SOM/AXEL ULite Hardware/Power and Reset/Power Supply Unit (PSU) and recommended power-up sequence"
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| − | + | ==Introduction== | |
| − | + | AXELULite system-on-module (SOM for short) is powered by carrier board via <code>VIN_SOM</code> rail. | |
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| − | + | About voltage range, three supported configurations are available. These configurations are indicated by the value of the '''f''' field of the ordering code. The generic ordering code is in the form | |
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| − | About voltage range, three supported configurations are available. These configurations are indicated by the value of the '''f''' field of the ordering code. The generic ordering code is in the form | ||
<center><code>DA p l r n c '''f''' t s</code></center> | <center><code>DA p l r n c '''f''' t s</code></center> | ||
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*3: power supply voltage range is 3.25 - 3.465V (that us 3.3 +5%/-1.5%). | *3: power supply voltage range is 3.25 - 3.465V (that us 3.3 +5%/-1.5%). | ||
| − | + | == Power Supply Unit (PSU) and recommended power-up sequence == | |
| − | + | Implementing correct power-up sequence for i.MX6UL processors is not a trivial task because several power rails are involved. AXELULite SOM simplifies this task by embedding all the needed circuitry. The following picture shows a simplified block diagram of PSU/voltage monitoring circuitry: | |
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| − | Implementing correct power-up sequence for i.MX6UL processors is not a trivial task because several power rails are involved. | ||
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| + | [[File:AxelLite-power-sequence.png | 800px]] | ||
The PSU is composed of two main blocks: | The PSU is composed of two main blocks: | ||
| − | * power management integrated circuit (PMIC NXP | + | * power management integrated circuit (PMIC, NXP PF0100E0 - on request this part is available in automotive grade) |
| − | * additional circuitry that completes PMIC functionalities. | + | * additional generic power management circuitry that completes PMIC functionalities. |
The PSU: | The PSU: | ||
| − | * generates the proper power-up sequence required by i. | + | * generates the proper power-up sequence required by i.MX processor and surrounding memories and peripherals |
| − | * synchronizes the powering up of carrier board in order to prevent back power | + | * synchronizes the powering up of carrier board in order to prevent back power |
| + | * provides some spare regulated voltages that can be used to power carrier board devices | ||
| − | + | === Power-up sequence=== | |
The typical power-up sequence is the following: | The typical power-up sequence is the following: | ||
| − | # (optional) PMIC_LICELL is powered | + | # (optional) PMIC_LICELL is powered |
| − | # | + | # 3.3VIN main power supply rail is powered |
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# CPU_PORn (active-low) is driven low | # CPU_PORn (active-low) is driven low | ||
| + | # PMIC activates PMIC_VSNVS power output | ||
# PMIC_PWRON signal is pulled-up (unless carrier board circuitry keeps this signal low for any reason) | # PMIC_PWRON signal is pulled-up (unless carrier board circuitry keeps this signal low for any reason) | ||
# PMIC transitions from OFF to ON state | # PMIC transitions from OFF to ON state | ||
| − | # PMIC initiates power-up sequence | + | # PMIC initiates power-up sequence needed by MX6 processor |
| − | # | + | # BOARD_PGOOD signal is raised; this active-high signal indicates that SoM's I/O is powered. This signal can be used to manage carrier board power up sequence in order to prevent back powering (from SoM to carrier board or vice versa). For additional information, please refer to the [[Power_(AxelLite)#Note_on_BOARD_PGOOD_usage | Note]] below. |
# CPU_PORn is released. | # CPU_PORn is released. | ||
| − | + | ==== Note on BOARD_PGOOD usage ==== | |
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| + | BOARD_PGOOD is generally used on carrier board to drive loads such as DC/DC enable inputs or switch on/off control signals. Depending on the kind of such loads, BOARD_PGOOD might not be able to drive them properly. In these cases a simple 2-input AND port can be used to address this issue. The following picture depicts a principle schematic showing this solution. VDD_SOM denotes the power rail used to power AXEL LITE SoM. | ||
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| + | [[File:Axel-lite-power-good.png]] | ||
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| + | === Power rails and related signals === | ||
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| + | The following list describes in detail the power rails and the power related signals. Please note that PMIC regulators ouput voltages can be changed only if explicitly allowed. | ||
| − | + | * 3.3VIN: this is external main power rail. Voltage range is 3.3V±5% | |
| − | + | * PMIC_CELL: PMIC's coin cell supply input/output | |
| + | * BOARD_PGOOD: this output signal is used to indicate when carrier board's circuitry interfacing Axel Lite's I/Os has to be powered up. | ||
| − | + | For further details, please refer to the PMIC documentation. | |
Revision as of 13:15, 14 July 2016
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Contents
Introduction[edit | edit source]
AXELULite system-on-module (SOM for short) is powered by carrier board via VIN_SOM rail.
About voltage range, three supported configurations are available. These configurations are indicated by the value of the f field of the ordering code. The generic ordering code is in the form
DA p l r n c f t sThe field f can assume the following values:
- 0, 1: power supply voltage range 3.135 - 3.465V (that is 3V3±5%)
- 2: power supply voltage range is 3.3 - 4.5V
- please note that this range can be widened by the use of an external MOSFET; for more details please refer to technical support
- 3: power supply voltage range is 3.25 - 3.465V (that us 3.3 +5%/-1.5%).
Power Supply Unit (PSU) and recommended power-up sequence[edit | edit source]
Implementing correct power-up sequence for i.MX6UL processors is not a trivial task because several power rails are involved. AXELULite SOM simplifies this task by embedding all the needed circuitry. The following picture shows a simplified block diagram of PSU/voltage monitoring circuitry:
The PSU is composed of two main blocks:
- power management integrated circuit (PMIC, NXP PF0100E0 - on request this part is available in automotive grade)
- additional generic power management circuitry that completes PMIC functionalities.
The PSU:
- generates the proper power-up sequence required by i.MX processor and surrounding memories and peripherals
- synchronizes the powering up of carrier board in order to prevent back power
- provides some spare regulated voltages that can be used to power carrier board devices
Power-up sequence[edit | edit source]
The typical power-up sequence is the following:
- (optional) PMIC_LICELL is powered
- 3.3VIN main power supply rail is powered
- CPU_PORn (active-low) is driven low
- PMIC activates PMIC_VSNVS power output
- PMIC_PWRON signal is pulled-up (unless carrier board circuitry keeps this signal low for any reason)
- PMIC transitions from OFF to ON state
- PMIC initiates power-up sequence needed by MX6 processor
- BOARD_PGOOD signal is raised; this active-high signal indicates that SoM's I/O is powered. This signal can be used to manage carrier board power up sequence in order to prevent back powering (from SoM to carrier board or vice versa). For additional information, please refer to the Note below.
- CPU_PORn is released.
Note on BOARD_PGOOD usage[edit | edit source]
BOARD_PGOOD is generally used on carrier board to drive loads such as DC/DC enable inputs or switch on/off control signals. Depending on the kind of such loads, BOARD_PGOOD might not be able to drive them properly. In these cases a simple 2-input AND port can be used to address this issue. The following picture depicts a principle schematic showing this solution. VDD_SOM denotes the power rail used to power AXEL LITE SoM.
[edit | edit source]
The following list describes in detail the power rails and the power related signals. Please note that PMIC regulators ouput voltages can be changed only if explicitly allowed.
- 3.3VIN: this is external main power rail. Voltage range is 3.3V±5%
- PMIC_CELL: PMIC's coin cell supply input/output
- BOARD_PGOOD: this output signal is used to indicate when carrier board's circuitry interfacing Axel Lite's I/Os has to be powered up.
For further details, please refer to the PMIC documentation.
