Difference between revisions of "Programmable logic (Bora)"

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{{Applies To Bora}}
 
{{Applies To Bora}}
 
{{InfoBoxBottom}}
 
{{InfoBoxBottom}}
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<section begin=History/>
 
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{| style="border-collapse:collapse; "
 
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!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
 
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!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Version
 
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!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date
 
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!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes
 
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|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|{{oldid|14898|1.0.0}}
 
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|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Oct 2021
 
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|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|New documentation layout
 
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|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|1.0.1
 
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|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Mar 2022
 
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|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Updated Bank 34 pinout
 
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|}
 
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<section end=History/>
 
  
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<section begin=Body/>
+
== Introduction ==
−
== Programmable logic ==
 
  
 
The following paragraphs describe in detail the available PL I/O pins and how they are routed to the Bora connectors. The Zynq-7000 AP SoC is split into I/O banks to allow for flexibility in the choice of I/O standards, thus each table reports one bank configuration. Moreover, Bora design allows carrier board to power two PL banks in order to achieve complete flexibility in terms of I/O voltage levels too.
 
The following paragraphs describe in detail the available PL I/O pins and how they are routed to the Bora connectors. The Zynq-7000 AP SoC is split into I/O banks to allow for flexibility in the choice of I/O standards, thus each table reports one bank configuration. Moreover, Bora design allows carrier board to power two PL banks in order to achieve complete flexibility in terms of I/O voltage levels too.
Line 32: Line 13:
 
|-
 
|-
 
!FPGA Bank
 
!FPGA Bank
−
!Type
 
 
!I/O Voltage
 
!I/O Voltage
 
!Voltage Pins
 
!Voltage Pins
Line 38: Line 18:
 
|-
 
|-
 
|Bank 35
 
|Bank 35
−
|High range (HR)
 
 
|User defined<br>VIO=FPGA_VDDIO_BANK35<br>'''1.8 to 3.3V'''
 
|User defined<br>VIO=FPGA_VDDIO_BANK35<br>'''1.8 to 3.3V'''
 
|J1.2<br>J1.66<br>J1.67<br>J1.68
 
|J1.2<br>J1.66<br>J1.67<br>J1.68
Line 44: Line 23:
 
|-
 
|-
 
|Bank 34
 
|Bank 34
−
|High range (HR)
 
 
|Fixed<br>'''VIO=3.3 V'''
 
|Fixed<br>'''VIO=3.3 V'''
 
| -
 
| -
Line 50: Line 28:
 
|-
 
|-
 
|Bank 13
 
|Bank 13
−
|High range (HR)
 
 
|User defined<br>VIO=FPGA_VDDIO_BANK13<br>'''1.8 to 3.3V'''
 
|User defined<br>VIO=FPGA_VDDIO_BANK13<br>'''1.8 to 3.3V'''
 
|J3.95<br>J3.96<br>J3.97<br>J3.98<br>J3.99
 
|J3.95<br>J3.96<br>J3.97<br>J3.98<br>J3.99
Line 67: Line 44:
 
Highlighted rows are related to signals that are used for particular functions into the SOM.
 
Highlighted rows are related to signals that are used for particular functions into the SOM.
  
−
=== FPGA Bank 34 ===
+
== FPGA Bank 34 ==
 
The following table reports the available pins connected to bank 34:
 
The following table reports the available pins connected to bank 34:
  
Line 148: Line 125:
 
|-
 
|-
 
| IO_L3N_T0_DQS_34 || J2.17 ||  
 
| IO_L3N_T0_DQS_34 || J2.17 ||  
−
|- style="background:#FF6633;"
+
|-
−
| IO_L3P_T0_DQS_PUDC_B_34 || J2.15 || Internally connected to a 10kΩ pull-up
+
| IO_L3P_T0_DQS_PUDC_B_34 || J2.15 ||  
 
|-
 
|-
 
| IO_L4N_T0_34 || J2.20 ||  
 
| IO_L4N_T0_34 || J2.20 ||  
Line 158: Line 135:
 
|-
 
|-
 
| IO_L5P_T0_34 || J2.14 ||  
 
| IO_L5P_T0_34 || J2.14 ||  
−
|-
+
|- style="background:#FF6633;"
−
| IO_L6N_T0_VREF_34 || J2.11 ||
+
| IO_L6N_T0_VREF_34 || J2.11 || Internally used for SOM ID. Connected to a 10kΩ pull-up
 
|- style="background:#FF6633;"
 
|- style="background:#FF6633;"
 
| IO_L6P_T0_34 || J2.9 || Internally used as CAN_TX
 
| IO_L6P_T0_34 || J2.9 || Internally used as CAN_TX
Line 166: Line 143:
 
|-
 
|-
 
| IO_L7P_T1_34 || J2.8 ||  
 
| IO_L7P_T1_34 || J2.8 ||  
−
|-
+
|- style="background:#FF6633;"
−
| IO_L8N_T1_34 || J2.7 ||
+
| IO_L8N_T1_34 || J2.7 || Internally used for SOM ID. Connected to a 10kΩ pull-up
−
|-
+
|- style="background:#FF6633;"
−
| IO_L8P_T1_34 || J2.5 ||
+
| IO_L8P_T1_34 || J2.5 || Internally used for SOM ID. Connected to a 10kΩ pull-up
 
|-
 
|-
 
| IO_L9N_T1_DQS_34 || J2.6 ||  
 
| IO_L9N_T1_DQS_34 || J2.6 ||  
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|}
 
|}
  
−
Regarding power voltage, take into consideration that Bank 34 is fixed at 3.3V.
+
Regarding power voltage, take into consideration that Bank 35 is fixed at 3.3V. For routing details, please refer to [[Integration_guide_(Bora)#PL_bank_34 | PL Bank 34 routing]].
−
====Routing information====
 
−
Routing implemented on Bora SoM allows the use of bank 34's signals as differential pairs as well as single-ended lines. Signals are grouped as denoted by the following table that details routing rules on Bora module. No carrier board guidelines can be provided, because these are application-dependent.
 
−
 
 
−
Pairs are highlighted with different colors. When used as differential pairs, differential impedence is 100 Ohm. When used as single-ended signals, impedence is 50 Ohm.
 
−
 
 
−
{| class="wikitable" border="1"
 
−
| align="center" style="background:#f0f0f0;"|'''Bora pin name'''
 
−
| align="center" style="background:#f0f0f0;"|'''Individual trace length<br>[mils]'''
 
−
| align="center" style="background:#f0f0f0;"|'''Intra-pair match<br>[mils]'''
 
−
| align="center" style="background:#f0f0f0;"|'''Inter-pair match<br>[mils]'''
 
−
| align="center" style="background:#f0f0f0;"|'''Group name'''
 
−
|-
 
−
| IO_L1N_T0_34||align="center"|1751,37||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|-
 
−
| IO_L1P_T0_34||align="center"|1749,02||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|- style="background: gray"
 
−
| IO_L2N_T0_34||align="center"|1625,68||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|- style="background: gray"
 
−
| IO_L2P_T0_34||align="center"|1624,91||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|-
 
−
| IO_L4N_T0_34||align="center"|1581,72||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|-
 
−
| IO_L4P_T0_34||align="center"|1582,11||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|- style="background: gray"
 
−
| IO_L5N_T0_34||align="center"|1769,81||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|- style="background: gray"
 
−
| IO_L5P_T0_34||align="center"|1776,23||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|-
 
−
| IO_L7N_T1_34||align="center"|1566,52||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|-
 
−
| IO_L7P_T1_34||align="center"|1569,36||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|- style="background: gray"
 
−
| IO_L9N_T1_DQS_34||align="center"|1490,25||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|- style="background: gray"
 
−
| IO_L9P_T1_DQS_34||align="center"|1498,04||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|-
 
−
| IO_L10N_T1_34||align="center"|1516,97||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|-
 
−
| IO_L10P_T1_34||align="center"|1517,37||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|- style="background: gray"
 
−
| IO_L15N_T2_DQS_34||align="center"|1610,74||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|- style="background: gray"
 
−
| IO_L15P_T2_DQS_34||align="center"|1602,81||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|-
 
−
| IO_L16N_T2_34||align="center"|1601,55||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|-
 
−
| IO_L16P_T2_34||align="center"|1616,03||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|- style="background: gray"
 
−
| IO_L17N_T2_34||align="center"|1574,33||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|- style="background: gray"
 
−
| IO_L17P_T2_34||align="center"|1593,38||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|-
 
−
| IO_L18N_T2_34||align="center"|1740,11||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|-
 
−
| IO_L18P_T2_34||align="center"|1750,54||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|- style="background: gray"
 
−
| IO_L20N_T3_34||align="center"|1588,01||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|- style="background: gray"
 
−
| IO_L20P_T3_34||align="center"|1585,53||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|-
 
−
| IO_L21N_T3_DQS_34||align="center"|1567,1||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|-
 
−
| IO_L21P_T3_DQS_34||align="center"|1570,96||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|- style="background: gray"
 
−
| IO_L22N_T3_34||align="center"|1619,26||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|- style="background: gray"
 
−
| IO_L22P_T3_34||align="center"|1622,13||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|-
 
−
| IO_L23N_T3_34||align="center"|1769,71||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|-
 
−
| IO_L23P_T3_34||align="center"|1775,52||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|- style="background: gray"
 
−
| IO_L24N_T3_34||align="center"|1772,07||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|- style="background: gray"
 
−
| IO_L24P_T3_34||align="center"|1774,49||align="center"|25||align="center"|300||BANK34 Diff group 1
 
−
|-style="background: black"
 
−
| ''' '''||||||||
 
−
|-
 
−
| IO_L11N_T1_SRCC_34||align="center"|1817,43||align="center"|10||align="center"|50||BANK34 xRCC group
 
−
|-
 
−
| IO_L11P_T1_SRCC_34||align="center"|1823,9||align="center"|10||align="center"|50||BANK34 xRCC group
 
−
|- style="background: gray"
 
−
| IO_L12N_T1_MRCC_34||align="center"|1844,2||align="center"|10||align="center"|50||BANK34 xRCC group
 
−
|- style="background: gray"
 
−
| IO_L12P_T1_MRCC_34||align="center"|1841,36||align="center"|10||align="center"|50||BANK34 xRCC group
 
−
|-
 
−
| IO_L13N_T1_MRCC_34||align="center"|1811,51||align="center"|10||align="center"|50||BANK34 xRCC group
 
−
|-
 
−
| IO_L13P_T1_MRCC_34||align="center"|1818,58||align="center"|10||align="center"|50||BANK34 xRCC group
 
−
|- style="background: gray"
 
−
| IO_L14N_T2_SRCC_34||align="center"|1818,78||align="center"|10||align="center"|50||BANK34 xRCC group
 
−
|- style="background: gray"
 
−
| IO_L14P_T2_SRCC_34||align="center"|1822,02||align="center"|10||align="center"|50||BANK34 xRCC group
 
−
|-
 
−
|}
 
−
 
 
−
The following table lists other signals that are not explicitly routed as differential pairs. Please note that some of these signals are internally used and thus they may have stubs.
 
−
{| class="wikitable" border="1"
 
−
| align="center" style="background:#f0f0f0;"|'''Bora pin name'''
 
−
| align="center" style="background:#f0f0f0;"|'''Trace length<br>[mils]'''
 
−
| align="center" style="background:#f0f0f0;"|'''Stubs due to internal use'''
 
−
|-
 
−
| IO_0_34||align="center"|1643,08||yes (total length including stubs: 1900,20 mils)
 
−
|-
 
−
| IO_25_34||align="center"|1484,09||yes (total length including stubs: 1741,03 mils)
 
−
|-
 
−
| IO_L19N_T3_VREF_34||align="center"|1880,62||yes (total length including stubs: 1959,35 mils)
 
−
|-
 
−
| IO_L19P_T3_34||align="center"|1066,01||yes (total length including stubs: 1152,88 mils)
 
−
|-
 
−
| IO_L3N_T0_DQS_34||align="center"|1050,49||yes (total length including stubs: 1133,5 mils)
 
−
|-
 
−
| IO_L3P_T0_DQS_PUDC_B_34||align="center"|1201,39||yes (total length including stubs: 1385,82 mils)
 
−
|-
 
−
| IO_L6N_T0_VREF_34||align="center"|1347,42||no
 
−
|-
 
−
| IO_L6P_T0_34||align="center"|1583,33||yes (total length including stubs 1698,73: mils)
 
−
|-
 
−
| IO_L8N_T1_34||align="center"|1518,79||yes (total length including stubs 1730,58: mils)
 
−
|-
 
−
| IO_L8P_T1_34||align="center"|1212,67||yes (total length including stubs 1435,25: mils)
 
−
|-
 
−
|}
 
−
 
 
−
About power voltage, take into consideration that Bank 34 is fixed at 3.3V.
 
  
−
=== FPGA Bank 35 ===
+
== FPGA Bank 35 ==
 
The following table reports the available pins connected to bank 35:
 
The following table reports the available pins connected to bank 35:
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
Line 415: Line 267:
  
 
On Bora side, routing of bank 35 has been optimized to interface 16-bit DDR3 SDRAM memory devices, clocked at a maximum frequency of 400 MHz. Regarding power voltage, Bank 35 is configurable and must be powered by carrier board. Please note that some signals belonging to this bank can be configured alternatively as XADC auxiliary analog inputs. For routing details, please refer to [[Integration_guide_(Bora)#PL_bank_35 | PL Bank 35 routing]].
 
On Bora side, routing of bank 35 has been optimized to interface 16-bit DDR3 SDRAM memory devices, clocked at a maximum frequency of 400 MHz. Regarding power voltage, Bank 35 is configurable and must be powered by carrier board. Please note that some signals belonging to this bank can be configured alternatively as XADC auxiliary analog inputs. For routing details, please refer to [[Integration_guide_(Bora)#PL_bank_35 | PL Bank 35 routing]].
−
====Routing information====
 
−
On Bora side, routing of bank 35 has been optimized to interface 16-bit DDR3 SDRAM memory devices, clocked at a maximum frequency of 400 MHz.
 
−
Signals have been grouped in the following classes:
 
−
* FDDR_ADDR
 
−
* FDDR_CK
 
−
* FDDR_BYTE0
 
−
* FDDR_BYTE1
 
−
Some of them are differential pairs. These kind of signals are highlighted in dark grey in the following sections where, for each signal, detailed information are provided, related to routing rules implemented on Bora SoM and carrier board guidelines.
 
−
 
−
Following tables indicates general recommended rules for single-ended and differantial pairs on carrier board in terms of impedence and isolation.
 
−
 
−
Differential pairs:
 
−
{| class="wikitable" border="1"
 
−
| align="center" style="background:#f0f0f0;"|'''      '''
 
−
| align="center" style="background:#f0f0f0;"|''' Value '''
 
−
| align="center" style="background:#f0f0f0;"|'''  UOM '''
 
−
|-
 
−
| Common Mode impedance typ||align="center"|55||align="center"|Ohm
 
−
|-
 
−
| Differential Mode impedance typ||align="center"|100||align="center"|Ohm
 
−
|-
 
−
| Isolation||align="center"|4x||align="center"|gap
 
−
|-
 
−
|}
 
−
 
−
Single-ended signals:
 
−
{| class="wikitable" border="1"
 
−
| align="center" style="background:#f0f0f0;"|'''      '''
 
−
| align="center" style="background:#f0f0f0;"|''' Value '''
 
−
| align="center" style="background:#f0f0f0;"|'''  UOM '''
 
−
|-
 
−
| Common Mode impedance typ||align="center"|55||align="center"|Ohm
 
−
|-
 
−
| Isolation||align="center"|2x||align="center"|width
 
−
|-
 
−
|}
 
−
 
−
About power voltage, Bank 35 is configurable and must be powered by carrier board.
 
  
−
Please note that some signals belonging to this bank can be configured alternatively as XADC auxiliary analog
+
== FPGA Bank 13 (Zynq 7020 only) ==
−
inputs.
 
−
===== FDDR_ADDR class =====
 
−
Following table details routing rules implemented on Bora SoM and suggested carrier board guidelines for FDDR_ADDR class signals. The picture shows connection scheme and the nomenclature used in the table.
 
  
−
[[File:FDDR_ADDR.png|thumb|center|600px]]
+
N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pins must not be left open and must be connected anyway, either to ground or to an external I/O voltage as described in [[Programmable_logic_(Bora)#Introduction | I/O banks table]].
−
 
 
−
 
 
−
{| class="wikitable" border="1"
 
−
! align="center" style="background:#f0f0f0;" rowspan="2" | '''Bora pin name'''
 
−
! align="center" style="background:#f0f0f0;" rowspan="2" | '''Group name'''
 
−
! align="center" style="background:#f0f0f0;" rowspan="2" | '''Carrier board net name'''
 
−
! align="center" style="background:#f0f0f0;" colspan="3" | '''SoM routing rules and specifications'''
 
−
! align="center" style="background:#f0f0f0;" colspan="6" | '''Carrier board guidelines'''
 
−
|-
 
−
! align="center" style="background:#f0f0f0;" | '''Actual length<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;" | '''Max length match<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;" | '''Nominal max length<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;" | '''AD_A2 length match<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;" | '''AD_AT length match<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;" | '''AD_AS1 length match<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;" | '''AD_AS1 max length<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;" | '''AD_AT max length<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;" | '''AD_A2+AD_AS1 max length<br>[mils]'''
 
−
|-
 
−
|IO_L17N_T2_AD5N_35||FDDR_ADDR||FDDR_ADDR_3||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
 
−
|-
 
−
| IO_L20P_T3_AD6P_35||FDDR_ADDR||FDDR_BA_2||align="center"|1853,4||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
 
−
|-
 
−
| IO_L16N_T2_35||FDDR_ADDR||FDDR_ADDR_5||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
 
−
|-
 
−
| IO_L18N_T2_AD13N_35||FDDR_ADDR||FDDR_ADDR_1||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
 
−
|-
 
−
| IO_L24N_T3_AD15N_35||FDDR_ADDR||FDDR_CKE_0||align="center"|1834,3||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
 
−
|-
 
−
| IO_L23P_T3_35||FDDR_ADDR||FDDR_CAS_N||align="center"|1857,01||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
 
−
|-
 
−
| IO_L14N_T2_AD4N_SRCC_35||FDDR_ADDR||FDDR_ADDR_9||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
 
−
|-
 
−
| IO_L24P_T3_AD15P_35||FDDR_ADDR||FDDR_CS0_N||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
 
−
|-
 
−
| IO_L14P_T2_AD4P_SRCC_35||FDDR_ADDR||FDDR_ADDR_10||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
 
−
|-
 
−
| IO_L15P_T2_DQS_AD12P_35||FDDR_ADDR||FDDR_ADDR_8||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
 
−
|-
 
−
| IO_L15N_T2_DQS_AD12N_35||FDDR_ADDR||FDDR_ADDR_7||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
 
−
|-
 
−
| IO_L12N_T1_MRCC_35||FDDR_ADDR||FDDR_RESET_N||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
 
−
|-
 
−
| IO_L13P_T2_MRCC_35||FDDR_ADDR||FDDR_ADDR_12||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
 
−
|-
 
−
| IO_L13N_T2_MRCC_35||FDDR_ADDR||FDDR_ADDR_11||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
 
−
|-
 
−
| IO_25_35||FDDR_ADDR||FDDR_ODT_0||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
 
−
|-
 
−
| IO_L23N_T3_35||FDDR_ADDR||FDDR_WE_N||align="center"|1869,66||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
 
−
|-
 
−
| IO_L17P_T2_AD5P_35||FDDR_ADDR||FDDR_ADDR_4||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
 
−
|-
 
−
| IO_L22N_T3_AD7N_35||FDDR_ADDR||FDDR_RAS_N||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
 
−
|-
 
−
| IO_L20N_T3_AD6N_35||FDDR_ADDR||FDDR_BA_1||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
 
−
|-
 
−
| IO_L18P_T2_AD13P_35||FDDR_ADDR||FDDR_ADDR_2||align="center"|1853,7||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
 
−
|-
 
−
| IO_L16P_T2_35||FDDR_ADDR||FDDR_ADDR_6||align="center"|1832||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
 
−
|-
 
−
| IO_L22P_T3_AD7P_35||FDDR_ADDR||FDDR_BA_0||align="center"|1850,82||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
 
−
|-
 
−
| IO_L19P_T3_35||FDDR_ADDR||FDDR_ADDR_0||align="center"|1836,73||align="center"|80||align="center"|1912||align="center"|40||align="center"|100||align="center"|50||align="center"|60||align="center"|400||align="center"|2100
 
−
|-
 
−
|}
 
−
 
 
−
===== FDDR_CK class =====
 
−
Following table details routing rules implemented on Bora SoM and suggested carrier board guidelines for FDDR_CK class signals. The picture shows connection scheme and the nomenclature used in the table.
 
−
 
 
−
[[File:FDDR_CK.png|thumb|center|600px]]
 
−
 
 
−
{| class="wikitable" border="1"
 
−
! align="center" style="background:#f0f0f0;" rowspan="2" |'''Bora pin name'''
 
−
! align="center" style="background:#f0f0f0;" rowspan="2" |'''Group name'''
 
−
! align="center" style="background:#f0f0f0;" rowspan="2" |'''Carrier board net name'''
 
−
! align="center" style="background:#f0f0f0;" colspan="4" |'''SoM routing rules and specifications'''
 
−
! align="center" style="background:#f0f0f0;" colspan="8" |'''Carrier board guidelines'''
 
−
|-
 
−
! align="center" style="background:#f0f0f0;"|'''Actual length<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;"|'''Intra-pair match<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;"|'''Max length match (with respect to FDDR_ADDR group)<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;"|'''Nominal max length<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;"|'''Intra-pair match<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;"|'''CK_A2 pair match (with respect to FDDR_ADDR)<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;"|'''CK_AT intra-pair match<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;"|'''CK_AS1 match (with respect to FDDR_ADDR)<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;"|'''CK_AS1 max length<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;"|'''CK_AT maximum length<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;"|'''CK_AT pair match (with respect to FDDR_ADDR)<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;"|'''CK_A2+CK_AS1 max length<br>[mils]'''
 
−
|- style="background: gray"
 
−
| IO_L21P_T3_DQS_AD14P_35||FDDR_CK||FDDR_CK_P0||align="center"|1900,39||align="center"|5||align="center"|80||align="center"|1912||align="center"|10||align="center"|40||align="center"|5||align="center"|50||align="center"|60||align="center"|400||align="center"|100||align="center"|2100
 
−
|- style="background: gray"
 
−
| IO_L21N_T3_DQS_AD14N_35||FDDR_CK||FDDR_CK_N0||align="center"|1898,17||align="center"|5||align="center"|80||align="center"|1912||align="center"|10||align="center"|40||align="center"|5||align="center"|50||align="center"|60||align="center"|400||align="center"|100||align="center"|2100
 
−
|-
 
−
|}
 
−
 
 
−
===== FDDR_BYTE0 class =====
 
−
Following table details routing rules implemented on Bora SoM and suggested carrier board guidelines for FDDR_BYTE0 class signals.
 
−
 
 
−
{| class="wikitable" border="1"
 
−
! align="center" style="background:#f0f0f0;" rowspan="2" |'''Pin Name'''
 
−
! align="center" style="background:#f0f0f0;" rowspan="2" |'''Group name'''
 
−
! align="center" style="background:#f0f0f0;" rowspan="2" |'''Carrier board net name'''
 
−
! align="center" style="background:#f0f0f0;" colspan="4" |'''SoM routing rules and specifications'''
 
−
! align="center" style="background:#f0f0f0;" colspan="3" |'''Carrier board guidelines'''
 
−
|-
 
−
! align="center" style="background:#f0f0f0;"|'''Actual length<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;"|'''Max length match<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;"|'''Max inter-pair match length on SOM<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;"|'''Nominal max length<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;"|'''Group match (mandatory)<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;"|'''Intra-pair match (mandatory)<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;"|'''Max length<br>[mils]'''
 
−
|-
 
−
| IO_L2N_T0_AD8N_35||FDDR_BYTE0||FDDR_DQ_2||align="center"|1222,66||align="center"|15||align="center"|-||align="center"|1230||align="center"|25||align="center"|-||align="center"|CK_A2+CK_AS1(max)
 
−
|-
 
−
| IO_L6P_T0_35||FDDR_BYTE0||FDDR_DQ_7||align="center"|1219,68||align="center"|15||align="center"|-||align="center"|1230||align="center"|25||align="center"|-||align="center"|CK_A2+CK_AS1(max)
 
−
|-
 
−
| IO_L5P_T0_AD9P_35||FDDR_BYTE0||FDDR_DQ_5||align="center"|1226,42||align="center"|15||align="center"|-||align="center"|1230||align="center"|25||align="center"|-||align="center"|CK_A2+CK_AS1(max)
 
−
|-
 
−
| IO_L4P_T0_35||FDDR_BYTE0||FDDR_DQ_3||align="center"|1219,68||align="center"|15||align="center"|-||align="center"|1230||align="center"|25||align="center"|-||align="center"|CK_A2+CK_AS1(max)
 
−
|-
 
−
| IO_L2P_T0_AD8P_35||FDDR_BYTE0||FDDR_DQ_1||align="center"|1219,68||align="center"|15||align="center"|-||align="center"|1230||align="center"|25||align="center"|-||align="center"|CK_A2+CK_AS1(max)
 
−
|-
 
−
| IO_L1N_T0_AD0N_35||FDDR_BYTE0||FDDR_DQ_0||align="center"|1219,68||align="center"|15||align="center"|-||align="center"|1230||align="center"|25||align="center"|-||align="center"|CK_A2+CK_AS1(max)
 
−
|-
 
−
| IO_L4N_T0_35||FDDR_BYTE0||FDDR_DQ_4||align="center"|1219,68||align="center"|15||align="center"|-||align="center"|1230||align="center"|25||align="center"|-||align="center"|CK_A2+CK_AS1(max)
 
−
|-
 
−
| IO_L5N_T0_AD9N_35||FDDR_BYTE0||FDDR_DQ_6||align="center"|1219,68||align="center"|15||align="center"|-||align="center"|1230||align="center"|25||align="center"|-||align="center"|CK_A2+CK_AS1(max)
 
−
|-
 
−
| IO_L1P_T0_AD0P_35||FDDR_BYTE0||FDDR_DM_0||align="center"|1219,68||align="center"|15||align="center"|-||align="center"|1230||align="center"|25||align="center"|-||align="center"|CK_A2+CK_AS1(max)
 
−
|- style="background: gray"
 
−
| IO_L3P_T0_DQS_AD1P_35||FDDR_BYTE0||FDDR_DQS_P0||align="center"|1221,04||align="center"|15||align="center"|5||align="center"|1230||align="center"|25||align="center"|5||align="center"|CK_A2+CK_AS1(max)
 
−
|- style="background: gray"
 
−
| IO_L3N_T0_DQS_AD1N_35||FDDR_BYTE0||FDDR_DQS_N0||align="center"|1219,42||align="center"|15||align="center"|5||align="center"|1230||align="center"|25||align="center"|5||align="center"|CK_A2+CK_AS1(max)
 
−
|-
 
−
|}
 
−
 
 
−
===== FDDR_BYTE1 class =====
 
−
Following table details routing rules implemented on Bora SoM and suggested carrier board guidelines for FDDR_BYTE1 class signals.
 
−
 
 
−
{| class="wikitable" border="1"
 
−
! align="center" style="background:#f0f0f0;" rowspan="2" |'''Pin Name'''
 
−
! align="center" style="background:#f0f0f0;" rowspan="2" |'''Group name'''
 
−
! align="center" style="background:#f0f0f0;" rowspan="2" |'''Carrier board net name'''
 
−
! align="center" style="background:#f0f0f0;" colspan="4" |'''SoM routing rules and specifications'''
 
−
! align="center" style="background:#f0f0f0;" colspan="3" |'''Carrier board guidelines'''
 
−
|-
 
−
! align="center" style="background:#f0f0f0;"|'''Actual length<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;"|'''Max length match<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;"|'''Max inter-pair match length on SOM<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;"|'''Nominal max length<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;"|'''Group match (mandatory)<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;"|'''Intra-pair match (mandatory)<br>[mils]'''
 
−
! align="center" style="background:#f0f0f0;"|'''Max length<br>[mils]'''
 
−
|-
 
−
| IO_L10N_T1_AD11N_35||FDDR_BYTE1||FDDR_DQ_12||align="center"|1345,93||align="center"|15||align="center"|-||align="center"|1355||align="center"|20||align="center"|-||align="center"|CK_A2+CK_AS1(max)
 
−
|-
 
−
| IO_L10P_T1_AD11P_35||FDDR_BYTE1||FDDR_DQ_11||align="center"|1345,93||align="center"|15||align="center"|-||align="center"|1355||align="center"|20||align="center"|-||align="center"|CK_A2+CK_AS1(max)
 
−
|-
 
−
| IO_L11P_T1_SRCC_35||FDDR_BYTE1||FDDR_DQ_13||align="center"|1353,43||align="center"|15||align="center"|-||align="center"|1355||align="center"|20||align="center"|-||align="center"|CK_A2+CK_AS1(max)
 
−
|-
 
−
| IO_L12P_T1_MRCC_35||FDDR_BYTE1||FDDR_DQ_15||align="center"|1341,3||align="center"|15||align="center"|-||align="center"|1355||align="center"|20||align="center"|-||align="center"|CK_A2+CK_AS1(max)
 
−
|-
 
−
| IO_L11N_T1_SRCC_35||FDDR_BYTE1||FDDR_DQ_14||align="center"|1340||align="center"|15||align="center"|-||align="center"|1355||align="center"|20||align="center"|-||align="center"|CK_A2+CK_AS1(max)
 
−
|-
 
−
| IO_L8P_T1_AD10P_35||FDDR_BYTE1||FDDR_DQ_9||align="center"|1340||align="center"|15||align="center"|-||align="center"|1355||align="center"|20||align="center"|-||align="center"|CK_A2+CK_AS1(max)
 
−
|-
 
−
| IO_L7N_T1_AD2N_35||FDDR_BYTE1||FDDR_DQ_8||align="center"|1340||align="center"|15||align="center"|-||align="center"|1355||align="center"|20||align="center"|-||align="center"|CK_A2+CK_AS1(max)
 
−
|-
 
−
| IO_L8N_T1_AD10N_35||FDDR_BYTE1||FDDR_DQ_10||align="center"|1340||align="center"|15||align="center"|-||align="center"|1355||align="center"|20||align="center"|-||align="center"|CK_A2+CK_AS1(max)
 
−
|-
 
−
| IO_L7P_T1_AD2P_35||FDDR_BYTE1||FDDR_DM_1||align="center"|1345,93||align="center"|15||align="center"|-||align="center"|1355||align="center"|20||align="center"|-||align="center"|CK_A2+CK_AS1(max)
 
−
|- style="background: gray"
 
−
| IO_L9P_T1_DQS_AD3P_35||FDDR_BYTE1||FDDR_DQS_P1||align="center"|1354,26||align="center"|15||align="center"|5||align="center"|1355||align="center"|20||align="center"|5||align="center"|CK_A2+CK_AS1(max)
 
−
|- style="background: gray"
 
−
| IO_L9N_T1_DQS_AD3N_35||FDDR_BYTE1||FDDR_DQS_N1||align="center"|1350,66||align="center"|15||align="center"|5||align="center"|1355||align="center"|20||align="center"|5||align="center"|CK_A2+CK_AS1(max)
 
−
|-
 
−
|}
 
−
 
 
−
==== VREF ====
 
−
Recommendations:
 
−
* use a "T" connection as shown by following picture
 
−
* use 20+ mils trace
 
−
* place bypass capacitors as close as possible to power balls.
 
−
 
 
−
[[File:VREF.png|thumb|center|600px]]
 
−
 
 
−
==== Other signals ====
 
−
The following table lists other signals that do not follow specific routing rules.
 
−
{| class="wikitable" border="1"
 
−
| align="center" style="background:#f0f0f0;"|'''Bora pin name'''
 
−
| align="center" style="background:#f0f0f0;"|'''Trace length<br>[mils]'''
 
−
|-
 
−
| IO_0_35||align="center"|1171,03
 
−
|-
 
−
| IO_L19N_T3_VREF_35||align="center"|2053,07
 
−
|-
 
−
| IO_L6N_T0_VREF_35||align="center"|2295,83
 
−
|-
 
−
|}
 
−
 
 
−
===== Related Xilinx documentation =====
 
−
* [http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_0/ug586_7Series_MIS.pdf Xilinx Memory Interface Solutions UG586]
 
−
* [http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_0/ds176_7Series_MIS.pdf Xilinx Memory Interface Solutions Data Sheet]
 
−
 
 
−
=== FPGA Bank 13 (Zynq 7020 only) ===
 
−
 
 
−
N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, '''VDDIO_BANK13 pins must not be left open and must be connected anyway''', either to ground or to an external I/O voltage as described in [[Programmable_logic_(Bora)#Introduction | I/O banks table]].
 
  
 
The following table reports the available pins connected to bank 13:
 
The following table reports the available pins connected to bank 13:
Line 732: Line 332:
  
 
Regarding power voltage, Bank 13 is configurable and must be powered by carrier board. For routing details, please refer to [[Integration_guide_(Bora)#PL_bank_13_.28XC7Z020_only.29 | PL Bank 13 routing]].
 
Regarding power voltage, Bank 13 is configurable and must be powered by carrier board. For routing details, please refer to [[Integration_guide_(Bora)#PL_bank_13_.28XC7Z020_only.29 | PL Bank 13 routing]].
−
====Routing information====
 
−
Routing implemented on Bora SoM allows the use of bank 13's signals as differential pairs as well as single-ended lines. Signals are grouped as denoted by the following table that details routing rules on Bora module. No carrier board guidelines can be provided, because these are application-dependent.
 
−
 
−
Pairs are highlighted with different colors. When used as differential pairs, differential impedence is 100 Ohm. When used as single-ended signals, impedence is 50 Ohm.
 
−
 
−
{| class="wikitable" border="1"
 
−
| align="center" style="background:#f0f0f0;"|'''Bora pin name'''
 
−
| align="center" style="background:#f0f0f0;"|'''Individual net length<br>[mils]'''
 
−
| align="center" style="background:#f0f0f0;"|'''Intra-pair match<br>[mils]'''
 
−
| align="center" style="background:#f0f0f0;"|'''Inter-pair match<br>[mils]'''
 
−
| align="center" style="background:#f0f0f0;"|'''Group Name'''
 
−
|-
 
−
| IO_L15N_T2_DQS_13||align="center"|1582,37||align="center"|25||align="center"|200||BANK13 Diff group 1
 
−
|-
 
−
| IO_L15P_T2_DQS_13||align="center"|1602,37||align="center"|25||align="center"|200||BANK13 Diff group 1
 
−
|- style="background: gray"
 
−
| IO_L16N_T2_13||align="center"|1589,32||align="center"|25||align="center"|200||BANK13 Diff group 1
 
−
|- style="background: gray"
 
−
| IO_L16P_T2_13||align="center"|1602,33||align="center"|25||align="center"|200||BANK13 Diff group 1
 
−
|-
 
−
| IO_L17N_T2_13||align="center"|1710,41||align="center"|25||align="center"|200||BANK13 Diff group 1
 
−
|-
 
−
| IO_L17P_T2_13||align="center"|1722,73||align="center"|25||align="center"|200||BANK13 Diff group 1
 
−
|- style="background: gray"
 
−
| IO_L18N_T2_13||align="center"|1720,53||align="center"|25||align="center"|200||BANK13 Diff group 1
 
−
|- style="background: gray"
 
−
| IO_L18P_T2_13||align="center"|1712,11||align="center"|25||align="center"|200||BANK13 Diff group 1
 
−
|-
 
−
| IO_L19N_T3_VREF_13||align="center"|1585,55||align="center"|25||align="center"|200||BANK13 Diff group 1
 
−
|-
 
−
| IO_L19P_T3_13||align="center"|1602,96||align="center"|25||align="center"|200||BANK13 Diff group 1
 
−
|- style="background: gray"
 
−
| IO_L20N_T3_13||align="center"|1623,95||align="center"|25||align="center"|200||BANK13 Diff group 1
 
−
|- style="background: gray"
 
−
| IO_L20P_T3_13||align="center"|1626,27||align="center"|25||align="center"|200||BANK13 Diff group 1
 
−
|-
 
−
| IO_L21N_T3_DQS_13||align="center"|1661,55||align="center"|25||align="center"|200||BANK13 Diff group 1
 
−
|-
 
−
| IO_L21P_T3_DQS_13||align="center"|1668,95||align="center"|25||align="center"|200||BANK13 Diff group 1
 
−
|- style="background: gray"
 
−
| IO_L22N_T3_13||align="center"|1592,18||align="center"|25||align="center"|200||BANK13 Diff group 1
 
−
|- style="background: gray"
 
−
| IO_L22P_T3_13||align="center"|1577,63||align="center"|25||align="center"|200||BANK13 Diff group 1
 
−
|-style="background: black"
 
−
| ''' '''||||||||
 
−
|-
 
−
| IO_L11N_T1_SRCC_13||align="center"|1702,04||align="center"|10||align="center"|50||BANK13  xRCC group
 
−
|-
 
−
| IO_L11P_T1_SRCC_13||align="center"|1705,07||align="center"|10||align="center"|50||BANK13  xRCC group
 
−
|- style="background: gray"
 
−
| IO_L12N_T1_MRCC_13||align="center"|1704,42||align="center"|10||align="center"|50||BANK13  xRCC group
 
−
|- style="background: gray"
 
−
| IO_L12P_T1_MRCC_13||align="center"|1703,11||align="center"|10||align="center"|50||BANK13  xRCC group
 
−
|-
 
−
| IO_L13N_T2_MRCC_13||align="center"|1731,33||align="center"|10||align="center"|50||BANK13  xRCC group
 
−
|-
 
−
| IO_L13P_T2_MRCC_13||align="center"|1732,15||align="center"|10||align="center"|50||BANK13  xRCC group
 
−
|- style="background: gray"
 
−
| IO_L14N_T2_SRCC_13||align="center"|1710,12||align="center"|10||align="center"|50||BANK13  xRCC group
 
−
|- style="background: gray"
 
−
| IO_L14P_T2_SRCC_13||align="center"|1716,36||align="center"|10||align="center"|50||BANK13  xRCC group
 
−
|-
 
−
|}
 
−
 
−
==== Other signals ====
 
−
The following table lists other signals that do not follow specific routing rules.
 
−
{| class="wikitable" border="1"
 
−
| align="center" style="background:#f0f0f0;"|'''Bora pin name'''
 
−
| align="center" style="background:#f0f0f0;"|'''Trace length<br>[mils]'''
 
−
|-
 
−
| IO_L6N_T0_VREF_13||align="center"|1098,15
 
−
|-
 
−
|}
 
−
<section end=Body/>
 

Revision as of 11:23, 29 January 2015

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Info Box
Bora5-small.jpg Applies to Bora

Introduction[edit | edit source]

The following paragraphs describe in detail the available PL I/O pins and how they are routed to the Bora connectors. The Zynq-7000 AP SoC is split into I/O banks to allow for flexibility in the choice of I/O standards, thus each table reports one bank configuration. Moreover, Bora design allows carrier board to power two PL banks in order to achieve complete flexibility in terms of I/O voltage levels too. For more details about PCB design considerations, please refer to the Advanced routing and carrier board design guidelines article.

The following table reports the I/O banks characteristics:

FPGA Bank I/O Voltage Voltage Pins Notes
Bank 35 User defined
VIO=FPGA_VDDIO_BANK35
1.8 to 3.3V 		J1.2
J1.66
J1.67
J1.68
Bank 34 Fixed
VIO=3.3 V 		-
Bank 13 User defined
VIO=FPGA_VDDIO_BANK13
1.8 to 3.3V 		J3.95
J3.96
J3.97
J3.98
J3.99 		Bank 13 is available only with Zynq XC7Z020 part number. Although this bank is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pins must not be left open and must be connected anyway, either to ground or to an external I/O voltage.

Each user I/O is labeled IO_LXXY_Tn_ZZZ_ADi_#, where:

  • IO indicates a user I/O pin.
  • L indicates a differential pair, with XX a unique pair in the bank and Y = [P|N] for the positive/negative sides of the differential pair.
  • Tn indicates the memory byte group [0-3]
  • ZZZ indicates a MRCC, SRCC or DQS pin
  • ADi indicates a XADC (analog-to-digital converter) differential auxiliary analog input [0–15].
  • # indicates the bank number.

Highlighted rows are related to signals that are used for particular functions into the SOM.

FPGA Bank 34[edit | edit source]

The following table reports the available pins connected to bank 34:

Pin Name Conn. Pin Notes
IO_0_34 J2.69
IO_25_34 J2.67
IO_L10N_T1_34 J2.65
IO_L10P_T1_34 J2.63
IO_L11N_T1_SRCC_34 J2.59
IO_L11P_T1_SRCC_34 J2.57
IO_L12N_T1_MRCC_34 J2.62
IO_L12P_T1_MRCC_34 J2.60
IO_L13N_T2_MRCC_34 N.A.
IO_L13P_T2_MRCC_34 N.A.
IO_L14N_T2_SRCC_34 J2.56
IO_L14P_T2_SRCC_34 J2.54
IO_L15N_T2_DQS_34 J2.47
IO_L15P_T2_DQS_34 J2.45
IO_L16N_T2_34 J2.50
IO_L16P_T2_34 J2.48
IO_L17N_T2_34 J2.46
IO_L17P_T2_34 J2.44
IO_L18N_T2_34 J2.41
IO_L18P_T2_34 J2.39
IO_L19N_T3_VREF_34 J2.37
IO_L19P_T3_34 J2.35 Internally used as CAN_RX
IO_L1N_T0_34 J2.40
IO_L1P_T0_34 J2.38
IO_L20N_T3_34 J2.36
IO_L20P_T3_34 J2.34
IO_L21N_T3_DQS_34 J2.31
IO_L21P_T3_DQS_34 J2.29
IO_L22N_T3_34 J2.27
IO_L22P_T3_34 J2.25
IO_L23N_T3_34 J2.30
IO_L23P_T3_34 J2.28
IO_L24N_T3_34 J2.26
IO_L24P_T3_34 J2.24
IO_L2N_T0_34 J2.21
IO_L2P_T0_34 J2.19
IO_L3N_T0_DQS_34 J2.17
IO_L3P_T0_DQS_PUDC_B_34 J2.15
IO_L4N_T0_34 J2.20
IO_L4P_T0_34 J2.18
IO_L5N_T0_34 J2.16
IO_L5P_T0_34 J2.14
IO_L6N_T0_VREF_34 J2.11 Internally used for SOM ID. Connected to a 10kΩ pull-up
IO_L6P_T0_34 J2.9 Internally used as CAN_TX
IO_L7N_T1_34 J2.10
IO_L7P_T1_34 J2.8
IO_L8N_T1_34 J2.7 Internally used for SOM ID. Connected to a 10kΩ pull-up
IO_L8P_T1_34 J2.5 Internally used for SOM ID. Connected to a 10kΩ pull-up
IO_L9N_T1_DQS_34 J2.6
IO_L9P_T1_DQS_34 J2.4

Regarding power voltage, take into consideration that Bank 35 is fixed at 3.3V. For routing details, please refer to PL Bank 34 routing.

FPGA Bank 35[edit | edit source]

The following table reports the available pins connected to bank 35:

Pin Name Conn. Pin Notes
IO_0_35 J1.74
IO_25_35 J1.18
IO_L10N_T1_AD11N_35 J1.6
IO_L10P_T1_AD11P_35 J1.5
IO_L11N_T1_SRCC_35 J1.10
IO_L11P_T1_SRCC_35 J1.7
IO_L12N_T1_MRCC_35 J1.27
IO_L12P_T1_MRCC_35 J1.8
IO_L13N_T2_MRCC_35 J1.39
IO_L13P_T2_MRCC_35 J1.40
IO_L14N_T2_AD4N_SRCC_35 J1.36
IO_L14P_T2_AD4P_SRCC_35 J1.34
IO_L15N_T2_DQS_AD12N_35 J1.47
IO_L15P_T2_DQS_AD12P_35 J1.46
IO_L16N_T2_35 J1.44
IO_L16P_T2_35 J1.45
IO_L17N_T2_AD5N_35 J1.37
IO_L17P_T2_AD5P_35 J1.32
IO_L18N_T2_AD13N_35 J1.42
IO_L18P_T2_AD13P_35 J1.43
IO_L19N_T3_VREF_35 J1.64
IO_L19P_T3_35 J1.41
IO_L1N_T0_AD0N_35 J1.53
IO_L1P_T0_AD0P_35 J1.50
IO_L20N_T3_AD6N_35 J1.23
IO_L20P_T3_AD6P_35 J1.21
IO_L21N_T3_DQS_AD14N_35 J1.33
IO_L21P_T3_DQS_AD14P_35 J1.31
IO_L22N_T3_AD7N_35 J1.26
IO_L22P_T3_AD7P_35 J1.25
IO_L23N_T3_35 J1.22
IO_L23P_T3_35 J1.28
IO_L24N_T3_AD15N_35 J1.16
IO_L24P_T3_AD15P_35 J1.20
IO_L2N_T0_AD8N_35 J1.51
IO_L2P_T0_AD8P_35 J1.52
IO_L3N_T0_DQS_AD1N_35 J1.63
IO_L3P_T0_DQS_AD1P_35 J1.61
IO_L4N_T0_35 J1.54
IO_L4P_T0_35 J1.56
IO_L5N_T0_AD9N_35 J1.55
IO_L5P_T0_AD9P_35 J1.57
IO_L6N_T0_VREF_35 J1.62
IO_L6P_T0_35 J1.58
IO_L7N_T1_AD2N_35 J1.11
IO_L7P_T1_AD2P_35 J1.3
IO_L8N_T1_AD10N_35 J1.9
IO_L8P_T1_AD10P_35 J1.12
IO_L9N_T1_DQS_AD3N_35 J1.17
IO_L9P_T1_DQS_AD3P_35 J1.15


On Bora side, routing of bank 35 has been optimized to interface 16-bit DDR3 SDRAM memory devices, clocked at a maximum frequency of 400 MHz. Regarding power voltage, Bank 35 is configurable and must be powered by carrier board. Please note that some signals belonging to this bank can be configured alternatively as XADC auxiliary analog inputs. For routing details, please refer to PL Bank 35 routing.

FPGA Bank 13 (Zynq 7020 only)[edit | edit source]

N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pins must not be left open and must be connected anyway, either to ground or to an external I/O voltage as described in I/O banks table.

The following table reports the available pins connected to bank 13:

Pin Name Conn. Pin Notes
IO_L11N_T1_SRCC_13 J3.136
IO_L11P_T1_SRCC_13 J3.134
IO_L12N_T1_MRCC_13 J3.137
IO_L12P_T1_MRCC_13 J3.135
IO_L13N_T2_MRCC_13 J3.130
IO_L13P_T2_MRCC_13 J3.128
IO_L14N_T2_SRCC_13 J3.131
IO_L14P_T2_SRCC_13 J3.129
IO_L15N_T2_DQS_13 J3.124
IO_L15P_T2_DQS_13 J3.122
IO_L16N_T2_13 J3.125
IO_L16P_T2_13 J3.123
IO_L17N_T2_13 J3.118
IO_L17P_T2_13 J3.116
IO_L18N_T2_13 J3.119
IO_L18P_T2_13 J3.117
IO_L19N_T3_VREF_13 J3.113
IO_L19P_T3_13 J3.111
IO_L20N_T3_13 J3.112
IO_L20P_T3_13 J3.110
IO_L21N_T3_DQS_13 J3.107
IO_L21P_T3_DQS_13 J3.105
IO_L22N_T3_13 J3.106
IO_L22P_T3_13 J3.104
IO_L6N_T0_VREF_13 J3.100

Regarding power voltage, Bank 13 is configurable and must be powered by carrier board. For routing details, please refer to PL Bank 13 routing.

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