Difference between revisions of "AURA SOM/AURA Hardware/Pinout Table"

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(→‎Pinout Table EVEN pins declaration)
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! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
 
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
 
|-  
 
|-  
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! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |ID#
 
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
 
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
 
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
 
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
 
|-
 
|-
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |{{oldid|18728|2023/05/15}}
+
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |{{oldid|17891|17891}}
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |15/05/2023
 
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Preliminary version
 
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Preliminary version
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|-
 
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |{{oldid|18879|2023/10/23}}
 
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Final SOM release
 
−
|-
 
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |{{oldid|18983|2023/12/01}}
 
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Pinmux label fix
 
−
|-
 
−
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |2023/12/20
 
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! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |Pin labels renaming<br>Add pinmux spreadsheet download
 
 
|-
 
|-
 
|}
 
|}
Line 40: Line 33:
 
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to AURA pinout specifications. See the images below for reference:
 
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to AURA pinout specifications. See the images below for reference:
  
−
[[File:AURA-SOM_top-pin1-203.png|500px|thumb|AURA TOP view|none]]
+
[[File:AURA-top-pin1-203.png|500px|thumb|AURA TOP view|none]]
−
[[File:AURA-SOM_bottom-pin2-204.png|500px|thumb|AURA BOTTOM view|none]]
+
[[File:AURA-bottom-pin2-204.png|500px|thumb|AURA BOTTOM view|none]]
  
 
===Pinout table naming conventions ===
 
===Pinout table naming conventions ===
Line 63: Line 56:
 
* PMIC.<x> : pin connected to the Power Manager IC (NXP PCA9451A)
 
* PMIC.<x> : pin connected to the Power Manager IC (NXP PCA9451A)
 
* LAN.<x> : pin connected to the LAN PHY (Microchip LAN8830T-V)
 
* LAN.<x> : pin connected to the LAN PHY (Microchip LAN8830T-V)
 +
* NOR.<x>: pin connected to the flash NOR
 +
* SV.<x>: pin connected to voltage supervisor
 +
* MTR: pin connected to voltage monitors
 
|-
 
|-
 
|'''Ball/pin #'''  
 
|'''Ball/pin #'''  
Line 100: Line 96:
 
|3.3VIN
 
|3.3VIN
 
|3.3
 
|3.3
−
|See [[AURA_SOM/AURA_Hardware/Electrical_Thermal_and_Mechanical_Features/Operational_characteristics#Recommended_ratings|Operational_characteristics]] of the SoM wiki page
+
|See [[AURA_SOM/AXEL_Lite_Hardware/Electrical_Thermal_and_Mechanical_Features/Operational_characteristics#Recommended_ratings|Operational_characteristics]] of the SoM wiki page
 
|-
 
|-
 
|NVCC_3V3
 
|NVCC_3V3
 
|3.3
 
|3.3
−
|Voltage generated by the internal PSU. See [[AURA_SOM/AURA_Hardware/Power_and_Reset/Power_Supply_Unit_(PSU)_and_recommended_power-up_sequence | Power Supply Unit (PSU)]] wiki page
+
|Voltage generated by the internal PSU. See [[AURA_SOM/AXEL_Lite_Hardware/Power_and_Reset/Power_Supply_Unit_(PSU)_and_recommended_power-up_sequence | Power Supply Unit (PSU)]] wiki page
 +
|-
 +
|NVCC_GPIO
 +
|3.3
 +
|Voltage generated by the internal PSU. See [[AURA_SOM/AXEL_Lite_Hardware/Power_and_Reset/Power_Supply_Unit_(PSU)_and_recommended_power-up_sequence | Power Supply Unit (PSU)]] wiki page
 
|-
 
|-
 
|VDD_ANA_1V8
 
|VDD_ANA_1V8
Line 111: Line 111:
 
|-
 
|-
 
|}
 
|}
−
 
−
===Pinout table XLS file ===
 
−
For your convenience, please find a spreadsheet with the AURA/MIMX935x pinout and pinmux table [https://www.dave.eu/links/p/hdTvHz4xQ811bdtb here].
 
  
 
==Pinout Table ODD pins declaration ==
 
==Pinout Table ODD pins declaration ==
Line 334: Line 331:
 
|NVCC_3V3
 
|NVCC_3V3
 
|I
 
|I
−
|mounting option
 
 
|
 
|
 
|
 
|
 +
|(mounting option)
 
|-
 
|-
 
| rowspan="8" |J1.43
 
| rowspan="8" |J1.43
Line 342: Line 339:
 
| rowspan="8" |CPU.GPIO_IO06
 
| rowspan="8" |CPU.GPIO_IO06
 
| rowspan="8" |L20
 
| rowspan="8" |L20
−
| rowspan="8" |NVCC_3V3
+
| rowspan="8" |NVCC_GPIO
 
| rowspan="8" |IO
 
| rowspan="8" |IO
 
| rowspan="8" |
 
| rowspan="8" |
Line 349: Line 346:
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|TPM5_CH0
+
|TMP5.CH0
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|PDM_BIT_STREAM01
+
|PDM.BIT_STREAM[1]
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA02
+
|LCDIF.D[2]
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|SPI7_SOUT
+
|SPI7.SOUT
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|UART6_CTS_B
+
|UART6.CTS_B
 
|-
 
|-
 
|Pin ALT-6
 
|Pin ALT-6
−
|I2C7_SDA
+
|I2C7.SDA
 
|-
 
|-
 
|Pin ALT-7
 
|Pin ALT-7
−
|FLEXIO1_FLEXIO06
+
|FLEXIO1.FLEXIO[6]
 
|-
 
|-
 
| rowspan="8" |J1.45
 
| rowspan="8" |J1.45
Line 373: Line 370:
 
| rowspan="8" |CPU.GPIO_IO18
 
| rowspan="8" |CPU.GPIO_IO18
 
| rowspan="8" |R18
 
| rowspan="8" |R18
−
| rowspan="8" |NVCC_3V3
+
| rowspan="8" |NVCC_GPIO
 
| rowspan="8" |IO
 
| rowspan="8" |IO
 
| rowspan="8" |
 
| rowspan="8" |
Line 380: Line 377:
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|SAI3_RX_BCLK
+
|SAI3.RX_BCLK
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAM_DATA09
+
|ISI.D[9]
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA14
+
|LCDIF.D[14]
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|SPI5_PCS0
+
|SPI5.PCS0
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|SPI4_PCS0
+
|SPI4.PCS0
 
|-
 
|-
 
|Pin ALT-6
 
|Pin ALT-6
−
|TPM5_CH2
+
|TMP5.CH2
 
|-
 
|-
 
|Pin ALT-7
 
|Pin ALT-7
−
|FLEXIO1_FLEXIO18
+
|FLEXIO1.FLEXIO[18]
 
|-
 
|-
 
| rowspan="8" |J1.47
 
| rowspan="8" |J1.47
Line 404: Line 401:
 
| rowspan="8" |CPU.GPIO_IO09
 
| rowspan="8" |CPU.GPIO_IO09
 
| rowspan="8" |M21
 
| rowspan="8" |M21
−
| rowspan="8" |NVCC_3V3
+
| rowspan="8" |NVCC_GPIO
 
| rowspan="8" |IO
 
| rowspan="8" |IO
 
| rowspan="8" |
 
| rowspan="8" |
Line 411: Line 408:
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|SPI3_SIN
+
|SPI3.SIN
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAM_DATA03
+
|ISI.D[3]
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA05
+
|LCDIF.D[5]
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|TPM3_EXTCLK
+
|TMP3.EXTCLK
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|UART7_RX
+
|UART7.RX
 
|-
 
|-
 
|Pin ALT-6
 
|Pin ALT-6
−
|I2C7_SCL
+
|I2C7.SCL
 
|-
 
|-
 
|Pin ALT-7
 
|Pin ALT-7
−
|FLEXIO1_FLEXIO09
+
|FLEXIO1.FLEXIO[9]
 
|-
 
|-
 
| rowspan="8" |J1.49
 
| rowspan="8" |J1.49
Line 435: Line 432:
 
| rowspan="8" |CPU.GPIO_IO08
 
| rowspan="8" |CPU.GPIO_IO08
 
| rowspan="8" |M20
 
| rowspan="8" |M20
−
| rowspan="8" |NVCC_3V3
+
| rowspan="8" |NVCC_GPIO
 
| rowspan="8" |IO
 
| rowspan="8" |IO
 
| rowspan="8" |
 
| rowspan="8" |
Line 442: Line 439:
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|SPI3_SPCS0
+
|SPI3.SPCS0
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAM_DATA02
+
|ISI.D[2]
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA04
+
|LCDIF.D[4]
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|TPM6_CH0
+
|TMP6.CH0
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|UART7_TX
+
|UART7.TX
 
|-
 
|-
 
|Pin ALT-6
 
|Pin ALT-6
−
|I2C7_SDA
+
|I2C7.SDA
 
|-
 
|-
 
|Pin ALT-7
 
|Pin ALT-7
−
|FLEXIO1_FLEXIO08
+
|FLEXIO1.FLEXIO[8]
 
|-
 
|-
 
|J1.51
 
|J1.51
Line 472: Line 469:
 
|
 
|
 
|-
 
|-
−
| rowspan="6" |J1.53
+
| rowspan="7" |J1.53
−
| rowspan="6" |SAI1_TXFS
+
| rowspan="7" |SAI1_TXFS
−
| rowspan="6" |CPU.SAI1_TXFS//BOOT2
+
| rowspan="7" |CPU.SAI1_TXFS//BOOT2
−
| rowspan="6" |G21
+
| rowspan="7" |G21
−
| rowspan="6" |NVCC_AON
+
| rowspan="7" |NVCC_AON
−
| rowspan="6" |IO
+
| rowspan="7" |IO
−
| rowspan="6" |
+
| rowspan="7" |
 
|Pin ALT-0
 
|Pin ALT-0
−
|SAI1_TX_SYNC
+
|SAI1.TX_SYNC
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|SAI1_TX_DATA01
+
|SAI1.TX_DATA[1]
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|SPI1_PCS0
+
|SPI1.PCS0
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
Line 492: Line 489:
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|MQS1_LEFT
+
|MQS1.LEFT
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO1_IO11//BOOT_MODE[2]
+
|GPIO1_IO11
 +
|-
 +
|Pin ALT-6
 +
|BOOT_MODE[2]
 
|-
 
|-
 
| rowspan="8" |J1.55
 
| rowspan="8" |J1.55
Line 501: Line 501:
 
| rowspan="8" |CPU.GPIO_IO10
 
| rowspan="8" |CPU.GPIO_IO10
 
| rowspan="8" |N17
 
| rowspan="8" |N17
−
| rowspan="8" |NVCC_3V3
+
| rowspan="8" |NVCC_GPIO
 
| rowspan="8" |IO
 
| rowspan="8" |IO
 
| rowspan="8" |
 
| rowspan="8" |
Line 508: Line 508:
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|SPI3_SOUT
+
|SPI3.SOUT
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAM_DATA04
+
|ISI.D[4]
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA06
+
|LCDIF.D[6]
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|TPM4_EXTCLK
+
|TMP4.EXTCLK
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|UART7_CTS_B
+
|UART7.CTS_B
 
|-
 
|-
 
|Pin ALT-6
 
|Pin ALT-6
−
|I2C8_SDA
+
|I2C8.SDA
 
|-
 
|-
 
|Pin ALT-7
 
|Pin ALT-7
−
|FLEXIO1_FLEXIO10
+
|FLEXIO1.FLEXIO[10]
 
|-
 
|-
 
|J1.57
 
|J1.57
Line 542: Line 542:
 
| rowspan="8" |CPU.GPIO_IO11
 
| rowspan="8" |CPU.GPIO_IO11
 
| rowspan="8" |N18
 
| rowspan="8" |N18
−
| rowspan="8" |NVCC_3V3
+
| rowspan="8" |NVCC_GPIO
 
| rowspan="8" |IO
 
| rowspan="8" |IO
 
| rowspan="8" |
 
| rowspan="8" |
 
|Pin ALT-0
 
|Pin ALT-0
−
|GPIO2_IO11
+
|GPIO2_IO10
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|SPI3_SCLK
+
|SPI3.SCLK
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAM_DATA05
+
|ISI.D[5]
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA07
+
|LCDIF.D[7]
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|TPM5_EXTCLK
+
|TMP5.EXTCLK
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|UART7_RTS_B
+
|UART7.RTS_B
 
|-
 
|-
 
|Pin ALT-6
 
|Pin ALT-6
−
|I2C8_SCL
+
|I2C8.SCL
 
|-
 
|-
 
|Pin ALT-7
 
|Pin ALT-7
−
|FLEXIO1_FLEXIO11
+
|FLEXIO1.FLEXIO[11]
 
|-
 
|-
 
| rowspan="4" |J1.61
 
| rowspan="4" |J1.61
Line 573: Line 573:
 
| rowspan="4" |CPU.GPIO_IO11
 
| rowspan="4" |CPU.GPIO_IO11
 
| rowspan="4" |T16
 
| rowspan="4" |T16
−
| rowspan="4" |NVCC_3V3
+
| rowspan="4" |NVCC_GPIO
 
| rowspan="4" |IO
 
| rowspan="4" |IO
−
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
+
| rowspan="4" |
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC3_DATA0
+
|USDHC3.DATA0
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|FLEXSPI1_A_DATA00
+
|FLE_SPI.A_DATA[0]
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|FLEXIO1_FLEXIO22
+
|FLEXIO1.FLEXIO[22]
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
Line 592: Line 592:
 
| rowspan="4" |CPU.GPIO_IO11
 
| rowspan="4" |CPU.GPIO_IO11
 
| rowspan="4" |V14
 
| rowspan="4" |V14
−
| rowspan="4" |NVCC_3V3
+
| rowspan="4" |NVCC_GPIO
 
| rowspan="4" |IO
 
| rowspan="4" |IO
−
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
+
| rowspan="4" |
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC3_DATA1
+
|USDHC3.DATA1
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|FLEXSPI1_A_DATA01
+
|FLE_SPI.A_DATA[1]
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|FLEXIO1_FLEXIO23
+
|FLEXIO1.FLEXIO[23]
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
Line 611: Line 611:
 
| rowspan="4" |CPU.GPIO_IO12
 
| rowspan="4" |CPU.GPIO_IO12
 
| rowspan="4" |U14
 
| rowspan="4" |U14
−
| rowspan="4" |NVCC_3V3
+
| rowspan="4" |NVCC_GPIO
 
| rowspan="4" |IO
 
| rowspan="4" |IO
−
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
+
| rowspan="4" |
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC3_DATA2
+
|USDHC3.DATA2
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|FLEXSPI1_A_DATA02
+
|FLE_SPI.A_DATA[2]
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|FLEXIO1_FLEXIO24
+
|FLEXIO1.FLEXIO[24]
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
Line 630: Line 630:
 
| rowspan="4" |CPU.GPIO_IO13
 
| rowspan="4" |CPU.GPIO_IO13
 
| rowspan="4" |T14
 
| rowspan="4" |T14
−
| rowspan="4" |NVCC_3V3
+
| rowspan="4" |NVCC_GPIO
 
| rowspan="4" |IO
 
| rowspan="4" |IO
−
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
+
| rowspan="4" |
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC3_DATA3
+
|USDHC3.DATA3
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|FLEXSPI1_A_DATA03
+
|FLE_SPI.A_DATA[3]
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|FLEXIO1_FLEXIO25
+
|FLEXIO1.FLEXIO[25]
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
Line 649: Line 649:
 
| rowspan="4" |CPU.GPIO_IO21
 
| rowspan="4" |CPU.GPIO_IO21
 
| rowspan="4" |U16
 
| rowspan="4" |U16
−
| rowspan="4" |NVCC_3V3
+
| rowspan="4" |NVCC_GPIO
 
| rowspan="4" |IO
 
| rowspan="4" |IO
−
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
+
| rowspan="4" |
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC3_CMD
+
|USDHC3.CMD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|FLEXSPI1_A_SS0_B
+
|FLE_SPI.A_SS0_B
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|FLEXIO1_FLEXIO21
+
|FLEXIO1.FLEXIO[21]
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
Line 668: Line 668:
 
| rowspan="4" |CPU.GPIO_IO20
 
| rowspan="4" |CPU.GPIO_IO20
 
| rowspan="4" |V16
 
| rowspan="4" |V16
−
| rowspan="4" |NVCC_3V3
+
| rowspan="4" |NVCC_GPIO
 
| rowspan="4" |IO
 
| rowspan="4" |IO
−
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
+
| rowspan="4" |
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC3_CLK
+
|USDHC3.CLK
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|FLEXSPI1_A_SCLK
+
|FLE_SPI.A_SCLK
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|FLEXIO1_FLEXIO20
+
|FLEXIO1.FLEXIO[20]
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
Line 697: Line 697:
 
| rowspan="5" |CPU.SD2_DATA0
 
| rowspan="5" |CPU.SD2_DATA0
 
| rowspan="5" |Y18
 
| rowspan="5" |Y18
−
| rowspan="5" |NVCC_3V3
+
| rowspan="5" |NVCC_GPIO
 
| rowspan="5" |IO
 
| rowspan="5" |IO
 
| rowspan="5" |
 
| rowspan="5" |
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC2_DATA0
+
|USDHC2.DATA0
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|ENET1_1588_EVENT0_OUT
+
|ENET2.1588_EVENT0_OUT
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAN2_TX
+
|CAN2.TX
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|FLEXIO1_FLEXIO03
+
|FLEXIO1.FLEXIO[3]
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
Line 719: Line 719:
 
| rowspan="5" |CPU.SD2_DATA1
 
| rowspan="5" |CPU.SD2_DATA1
 
| rowspan="5" |AA18
 
| rowspan="5" |AA18
−
| rowspan="5" |NVCC_3V3
+
| rowspan="5" |NVCC_GPIO
 
| rowspan="5" |IO
 
| rowspan="5" |IO
 
| rowspan="5" |
 
| rowspan="5" |
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC2_DATA1
+
|USDHC2.DATA1
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|ENET1_1588_EVENT1_IN
+
|ENET2.1588_EVENT1_IN
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAN2_RX
+
|CAN2.RX
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|FLEXIO1_FLEXIO04
+
|FLEXIO1.FLEXIO[4]
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
Line 741: Line 741:
 
| rowspan="5" |CPU.SD2_DATA2
 
| rowspan="5" |CPU.SD2_DATA2
 
| rowspan="5" |Y20
 
| rowspan="5" |Y20
−
| rowspan="5" |NVCC_3V3
+
| rowspan="5" |NVCC_GPIO
 
| rowspan="5" |IO
 
| rowspan="5" |IO
 
| rowspan="5" |
 
| rowspan="5" |
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC2_DATA2
+
|USDHC2.DATA2
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|ENET1_1588_EVENT1_OUT
+
|ENET2.1588_EVENT1_OUT
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|MQS1_RIGHT
+
|MQS1.RIGHT
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|FLEXIO1_FLEXIO05
+
|FLEXIO1.FLEXIO[5]
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
Line 763: Line 763:
 
| rowspan="5" |CPU.SD2_DATA3
 
| rowspan="5" |CPU.SD2_DATA3
 
| rowspan="5" |AA20
 
| rowspan="5" |AA20
−
| rowspan="5" |NVCC_3V3
+
| rowspan="5" |NVCC_GPIO
 
| rowspan="5" |IO
 
| rowspan="5" |IO
 
| rowspan="5" |
 
| rowspan="5" |
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC2_DATA3
+
|USDHC2.DATA3
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|LPTMR2_ALT1
+
|LPTMR2.ALT1
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|MQS1_LEFT
+
|MQS1.LEFT
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|FLEXIO1_FLEXIO06
+
|FLEXIO1.FLEXIO[6]
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
Line 785: Line 785:
 
| rowspan="6" |CPU.SD2_CMD
 
| rowspan="6" |CPU.SD2_CMD
 
| rowspan="6" |Y19
 
| rowspan="6" |Y19
−
| rowspan="6" |NVCC_3V3
+
| rowspan="6" |NVCC_GPIO
 
| rowspan="6" |IO
 
| rowspan="6" |IO
 
| rowspan="6" |
 
| rowspan="6" |
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC2_CMD
+
|USDHC2.CMD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|ENET1_1588_EVENT0_IN
+
|ENET2.1588_EVENT0_IN
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|I3C2_PUR
+
|I3C2.PUR
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|I3C2_PUR_B
+
|I3C2.PUR_B
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|FLEXIO1_FLEXIO02
+
|FLEXIO1.FLEXIO[2]
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
Line 810: Line 810:
 
| rowspan="5" |CPU.SD2_CLK
 
| rowspan="5" |CPU.SD2_CLK
 
| rowspan="5" |AA19
 
| rowspan="5" |AA19
−
| rowspan="5" |NVCC_3V3
+
| rowspan="5" |NVCC_GPIO
 
| rowspan="5" |IO
 
| rowspan="5" |IO
 
| rowspan="5" |
 
| rowspan="5" |
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC2_CLK
+
|USDHC2.CLK
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|ENET_QOS_1588_EVENT0_OUT
+
|ENET_QOS.1588_EVENT0_OUT
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|I3C2_SDA
+
|I3C2.SDA
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|FLEXIO1_FLEXIO01
+
|FLEXIO1.FLEXIO[1]
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
Line 842: Line 842:
 
| rowspan="8" |CPU.GPIO_IO14
 
| rowspan="8" |CPU.GPIO_IO14
 
| rowspan="8" |P20
 
| rowspan="8" |P20
−
| rowspan="8" |NVCC_3V3
+
| rowspan="8" |NVCC_GPIO
 
| rowspan="8" |IO
 
| rowspan="8" |IO
 
| rowspan="8" |
 
| rowspan="8" |
Line 849: Line 849:
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|UART3_TX
+
|UART3.TX
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAM_DATA06
+
|ISI.D[6]
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA10
+
|LCDIF.D[10]
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|SPI8_SOUT
+
|SPI8.SOUT
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|UART8_CTS_B
+
|UART8.CTS_B
 
|-
 
|-
 
|Pin ALT-6
 
|Pin ALT-6
−
|UART4_TX
+
|UART4.TX
 
|-
 
|-
 
|Pin ALT-7
 
|Pin ALT-7
−
|FLEXIO1_FLEXIO14
+
|FLEXIO1.FLEXIO[14]
 
|-
 
|-
 
| rowspan="8" |J1.91
 
| rowspan="8" |J1.91
Line 873: Line 873:
 
| rowspan="8" |CPU.GPIO_IO15
 
| rowspan="8" |CPU.GPIO_IO15
 
| rowspan="8" |P21
 
| rowspan="8" |P21
−
| rowspan="8" |NVCC_3V3
+
| rowspan="8" |NVCC_GPIO
 
| rowspan="8" |IO
 
| rowspan="8" |IO
 
| rowspan="8" |
 
| rowspan="8" |
Line 880: Line 880:
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|UART3_RX
+
|UART3.RX
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAM_DATA07
+
|ISI.D[7]
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA11
+
|LCDIF.D[11]
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|SPI8_SCK
+
|SPI8.SCK
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|UART8_RTS_B
+
|UART8.RTS_B
 
|-
 
|-
 
|Pin ALT-6
 
|Pin ALT-6
−
|UART4_RX
+
|UART4.RX
 
|-
 
|-
 
|Pin ALT-7
 
|Pin ALT-7
−
|FLEXIO1_FLEXIO15
+
|FLEXIO1.FLEXIO[15]
 
|-
 
|-
 
| rowspan="5" |J1.93
 
| rowspan="5" |J1.93
Line 904: Line 904:
 
| rowspan="5" |CPU.UART2_TXD//BOOT1
 
| rowspan="5" |CPU.UART2_TXD//BOOT1
 
| rowspan="5" |F21
 
| rowspan="5" |F21
−
| rowspan="5" |NVCC_3V3
+
| rowspan="5" |NVCC_GPIO
 
| rowspan="5" |IO
 
| rowspan="5" |IO
−
| rowspan="5" |Used as default console for Cortex-M33
+
| rowspan="5" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|UART2_TX
 
|UART2_TX
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|UART1_RTS_B
+
|UART1.RTS_B
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|SPI2_SCK
+
|SPI2.SCK
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|TPM1_CH3
+
|TMP1.CH3
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
Line 926: Line 926:
 
| rowspan="6" |CPU.UART2_RXD
 
| rowspan="6" |CPU.UART2_RXD
 
| rowspan="6" |F20
 
| rowspan="6" |F20
−
| rowspan="6" |NVCC_3V3
+
| rowspan="6" |NVCC_GPIO
 
| rowspan="6" |IO
 
| rowspan="6" |IO
−
| rowspan="6" |Used as default console for Cortex-M33
+
| rowspan="6" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|UART2_RX
 
|UART2_RX
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|UART1_CTS_B
+
|UART1.CTS_B
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|SPI2_SOUT
+
|SPI2.SOUT
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|TPM1_CH2
+
|TMP1.CH2
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|SAI1_MCLK
+
|SAI1.MCLK
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
Line 951: Line 951:
 
| rowspan="5" |CPU.SD2_VSELECT
 
| rowspan="5" |CPU.SD2_VSELECT
 
| rowspan="5" |V18
 
| rowspan="5" |V18
−
| rowspan="5" |NVCC_3V3
+
| rowspan="5" |NVCC_GPIO
 
| rowspan="5" |IO
 
| rowspan="5" |IO
 
| rowspan="5" |
 
| rowspan="5" |
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC2_VSELECT
+
|USDHC2.VSELECT
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|USHDC2_WP
+
|USHDC2.WP
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|LPTMR2_ALT3
+
|LPTMR2.ALT3
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|FLEXIO1_FLEXIO19
+
|FLEXIO1.FLEXIO[19]
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
Line 973: Line 973:
 
| rowspan="4" |CPU.SD2_RESET_B
 
| rowspan="4" |CPU.SD2_RESET_B
 
| rowspan="4" |AA17
 
| rowspan="4" |AA17
−
| rowspan="4" |NVCC_3V3
+
| rowspan="4" |NVCC_GPIO
 
| rowspan="4" |IO
 
| rowspan="4" |IO
 
| rowspan="4" |
 
| rowspan="4" |
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC2_RESET_B
+
|USDHC2.RESET_B
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|LPTMR2_ALT2
+
|LPTMR2.ALT2
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|FLEXIO1_FLEXIO07
+
|FLEXIO1.FLEXIO[7]
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
Line 992: Line 992:
 
| rowspan="5" |CPU.I2C1_SCL
 
| rowspan="5" |CPU.I2C1_SCL
 
| rowspan="5" |C20
 
| rowspan="5" |C20
−
| rowspan="5" |NVCC_3V3
+
| rowspan="5" |NVCC_GPIO
 
| rowspan="5" |IO
 
| rowspan="5" |IO
 
| rowspan="5" |
 
| rowspan="5" |
 
|Pin ALT-0
 
|Pin ALT-0
−
|I2C1_SCL
+
|I2C1.SCL
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|I3C1_SCL
+
|I3C1.SCL
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|UART1_DCB_B
+
|UART1.DCB_B
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|TPM2_CH0
+
|TMP2.CH0
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
Line 1,014: Line 1,014:
 
| rowspan="5" |CPU.I2C1_SDA
 
| rowspan="5" |CPU.I2C1_SDA
 
| rowspan="5" |C21
 
| rowspan="5" |C21
−
| rowspan="5" |NVCC_3V3
+
| rowspan="5" |NVCC_GPIO
 
| rowspan="5" |IO
 
| rowspan="5" |IO
 
| rowspan="5" |
 
| rowspan="5" |
 
|Pin ALT-0
 
|Pin ALT-0
−
|I2C1_SDA
+
|I2C1.SDA
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|I3C1_SDA
+
|I3C1.SDA
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|UART1_RIN_B
+
|UART1.RIN_B
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|TPM2_CH1
+
|TMP2.CH1
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
Line 1,036: Line 1,036:
 
| rowspan="6" |CPU.SAI1_TXD0//BOOT3
 
| rowspan="6" |CPU.SAI1_TXD0//BOOT3
 
| rowspan="6" |H21
 
| rowspan="6" |H21
−
| rowspan="6" |NVCC_3V3
+
| rowspan="6" |NVCC_GPIO
 
| rowspan="6" |IO
 
| rowspan="6" |IO
 
| rowspan="6" |
 
| rowspan="6" |
 
|Pin ALT-0
 
|Pin ALT-0
−
|SAI1_TX_DATA00
+
|SAI1.TX_DATA[0]
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|UART2_RTS_B
+
|UART2.RTS_B
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|SPI1_SCK
+
|SPI1.SCK
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|UART1_DTR_B
+
|UART1.DTR_B
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|CAN1_TX
+
|CAN1.TX
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
Line 1,061: Line 1,061:
 
| rowspan="6" |CPU.SAI1_TXC
 
| rowspan="6" |CPU.SAI1_TXC
 
| rowspan="6" |G20
 
| rowspan="6" |G20
−
| rowspan="6" |NVCC_3V3
+
| rowspan="6" |NVCC_GPIO
 
| rowspan="6" |IO
 
| rowspan="6" |IO
 
| rowspan="6" |
 
| rowspan="6" |
 
|Pin ALT-0
 
|Pin ALT-0
−
|SAI1_TX_BCLK
+
|SAI1.TX_BCLK
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|UART2_CTS_B
+
|UART2.CTS_B
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|SPI1_SIN
+
|SPI1.SIN
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|UART1_DSR_B
+
|UART1.DSR_B
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|CAN1_RX
+
|CAN1.RX
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
Line 1,096: Line 1,096:
 
| rowspan="1" |CPU.ADC_IN0
 
| rowspan="1" |CPU.ADC_IN0
 
| rowspan="1" |B19
 
| rowspan="1" |B19
−
| rowspan="1" |NVCC_3V3
+
| rowspan="1" |NVCC_GPIO
 
| rowspan="1" |IO
 
| rowspan="1" |IO
 
| rowspan="1" |
 
| rowspan="1" |
 
|Pin ALT-0
 
|Pin ALT-0
−
|ADC_IN0
+
|ANAMIX.ADC_IN0
 
|-
 
|-
 
| rowspan="1" |J1.113
 
| rowspan="1" |J1.113
Line 1,106: Line 1,106:
 
| rowspan="1" |CPU.ADC_IN1
 
| rowspan="1" |CPU.ADC_IN1
 
| rowspan="1" |A20
 
| rowspan="1" |A20
−
| rowspan="1" |NVCC_3V3
+
| rowspan="1" |NVCC_GPIO
 
| rowspan="1" |IO
 
| rowspan="1" |IO
 
| rowspan="1" |
 
| rowspan="1" |
 
|Pin ALT-0
 
|Pin ALT-0
−
|ADC_IN1
+
|ANAMIX.ADC_IN1
 
|-
 
|-
 
| rowspan="1" |J1.115
 
| rowspan="1" |J1.115
Line 1,116: Line 1,116:
 
| rowspan="1" |CPU.ADC_IN2
 
| rowspan="1" |CPU.ADC_IN2
 
| rowspan="1" |B20
 
| rowspan="1" |B20
−
| rowspan="1" |NVCC_3V3
+
| rowspan="1" |NVCC_GPIO
 
| rowspan="1" |IO
 
| rowspan="1" |IO
 
| rowspan="1" |
 
| rowspan="1" |
 
|Pin ALT-0
 
|Pin ALT-0
−
|ADC_IN2
+
|ANAMIX.ADC_IN2
 
|-
 
|-
 
| rowspan="1" |J1.117
 
| rowspan="1" |J1.117
Line 1,126: Line 1,126:
 
| rowspan="1" |CPU.ADC_IN3
 
| rowspan="1" |CPU.ADC_IN3
 
| rowspan="1" |B21
 
| rowspan="1" |B21
−
| rowspan="1" |NVCC_3V3
+
| rowspan="1" |NVCC_GPIO
 
| rowspan="1" |IO
 
| rowspan="1" |IO
 
| rowspan="1" |
 
| rowspan="1" |
 
|Pin ALT-0
 
|Pin ALT-0
−
|ADC_IN3
+
|ANAMIX.ADC_IN3
 
|-
 
|-
 
|J1.119
 
|J1.119
Line 1,176: Line 1,176:
 
| rowspan="5" |CPU.I2C2_SDA<br>PMIC.SDA
 
| rowspan="5" |CPU.I2C2_SDA<br>PMIC.SDA
 
| rowspan="5" |D21<br>42
 
| rowspan="5" |D21<br>42
−
| rowspan="5" |NVCC_3V3
+
| rowspan="5" |NVCC_GPIO
 
| rowspan="5" |IO
 
| rowspan="5" |IO
 
| rowspan="5" |
 
| rowspan="5" |
 
|Pin ALT-0
 
|Pin ALT-0
−
|I2C2_SDA
+
|I2C2.SDA
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|UART2_RIN_B
+
|UART2.RIN_B
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|TPM2_CH3
+
|TMP2.CH3
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|SAI1_RX_BCLK
+
|SAI1.RX_BCLK
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
Line 1,198: Line 1,198:
 
| rowspan="7" |CPU.I2C2_SCL<br>PMIC.SCL
 
| rowspan="7" |CPU.I2C2_SCL<br>PMIC.SCL
 
| rowspan="7" |D20<br>41
 
| rowspan="7" |D20<br>41
−
| rowspan="7" |NVCC_3V3
+
| rowspan="7" |NVCC_GPIO
 
| rowspan="7" |IO
 
| rowspan="7" |IO
 
| rowspan="7" |
 
| rowspan="7" |
 
|Pin ALT-0
 
|Pin ALT-0
−
|I2C2_SCL
+
|I2C2.SCL
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|I3C1_PUR
+
|I3C1.PUR
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|UART2_DCB_B
+
|UART2.DCB_B
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|TPM2_CH2
+
|TMP2.CH2
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|SAI1_RX_SYNC
+
|SAI1.RX_SYNC
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
Line 1,220: Line 1,220:
 
|-
 
|-
 
|Pin ALT-6
 
|Pin ALT-6
−
|I3C1_PUR_B
+
|I3C1.PUR_B
 
|-
 
|-
 
|J1.131
 
|J1.131
Line 1,456: Line 1,456:
 
| rowspan="5" |CPU.GPIO_IO08
 
| rowspan="5" |CPU.GPIO_IO08
 
| rowspan="5" |M20
 
| rowspan="5" |M20
−
| rowspan="5" |NVCC_3V3
+
| rowspan="5" |NVCC_GPIO
 
| rowspan="5" |IO
 
| rowspan="5" |IO
 
| rowspan="5" |
 
| rowspan="5" |
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC2_CD_B
+
|USDHC2.CD_B
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|ENET_QOS_1588_EVENT0_IN
+
|ENET_QOS.1588_EVENT0_IN
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|I2C3_SCL
+
|I2C3.SCL
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|FLEXIO1_FLEXIO00
+
|FLEXIO1.FLEXIO[0]
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
Line 1,478: Line 1,478:
 
| rowspan="8" |CPU.GPIO_IO00
 
| rowspan="8" |CPU.GPIO_IO00
 
| rowspan="8" |J21
 
| rowspan="8" |J21
−
| rowspan="8" |NVCC_3V3
+
| rowspan="8" |NVCC_GPIO
 
| rowspan="8" |IO
 
| rowspan="8" |IO
 
| rowspan="8" |
 
| rowspan="8" |
Line 1,485: Line 1,485:
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|I2C3_SDA
+
|I2C3.SDA
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAM_CLK
+
|ISI.PCLK
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_CLK
+
|LCDIF.PCLK
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|SPI6_PCS0
+
|SPI6.PCS0
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|UART5_TX
+
|UART5.TX
 
|-
 
|-
 
|Pin ALT-6
 
|Pin ALT-6
−
|I2C5_SDA
+
|I2C5.SDA
 
|-
 
|-
 
|Pin ALT-7
 
|Pin ALT-7
−
|FLEXIO1_FLEXIO00
+
|FLEXIO1.FLEXIO[0]
 
|-
 
|-
 
| rowspan="8" |J1.181
 
| rowspan="8" |J1.181
Line 1,509: Line 1,509:
 
| rowspan="8" |CPU.GPIO_IO03
 
| rowspan="8" |CPU.GPIO_IO03
 
| rowspan="8" |K21
 
| rowspan="8" |K21
−
| rowspan="8" |NVCC_3V3
+
| rowspan="8" |NVCC_GPIO
 
| rowspan="8" |IO
 
| rowspan="8" |IO
 
| rowspan="8" |
 
| rowspan="8" |
Line 1,516: Line 1,516:
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|I2C4_SCL
+
|I2C4.SCL
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAM_HSYNC
+
|ISI.LINE_VALID
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_HSYNC
+
|LCDIF.HSYNC
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|SPI6_SCK
+
|SPI6.SCK
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|UART5_RTS_B
+
|UART5.RTS_B
 
|-
 
|-
 
|Pin ALT-6
 
|Pin ALT-6
−
|I2C6_SCL
+
|I2C6.SCL
 
|-
 
|-
 
|Pin ALT-7
 
|Pin ALT-7
−
|FLEXIO1_FLEXIO03
+
|FLEXIO1.FLEXIO[3]
 
|-
 
|-
 
| rowspan="8" |J1.183
 
| rowspan="8" |J1.183
Line 1,540: Line 1,540:
 
| rowspan="8" |CPU.GPIO_IO01
 
| rowspan="8" |CPU.GPIO_IO01
 
| rowspan="8" |K21
 
| rowspan="8" |K21
−
| rowspan="8" |NVCC_3V3
+
| rowspan="8" |NVCC_GPIO
 
| rowspan="8" |IO
 
| rowspan="8" |IO
 
| rowspan="8" |
 
| rowspan="8" |
Line 1,547: Line 1,547:
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|I2C3_SCL
+
|I2C3.SCL
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAM_DATA00
+
|ISI.D[0]
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DE
+
|LCDIF.DE
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|SPI6_SIN
+
|SPI6.SIN
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|UART5_RX
+
|UART5.RX
 
|-
 
|-
 
|Pin ALT-6
 
|Pin ALT-6
−
|I2C5_SCL
+
|I2C5.SCL
 
|-
 
|-
 
|Pin ALT-7
 
|Pin ALT-7
−
|FLEXIO1_FLEXIO01
+
|FLEXIO1.FLEXIO[1]
 
|-
 
|-
 
|J1.185
 
|J1.185
Line 1,579: Line 1,579:
 
| rowspan="5" |J1.187
 
| rowspan="5" |J1.187
 
| rowspan="5" |UART1_TXD
 
| rowspan="5" |UART1_TXD
−
| rowspan="5" |CPU.UART1_TXD//BOOT0
+
| rowspan="5" |CPU.UART1_TXD//BOOT_MODE0
 
| rowspan="5" |E21
 
| rowspan="5" |E21
−
| rowspan="5" |NVCC_3V3
+
| rowspan="5" |NVCC_GPIO
 
| rowspan="5" |IO
 
| rowspan="5" |IO
−
| rowspan="5" |Used as default Linux console (Cortex-A55)
+
| rowspan="5" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|UART1_TX
 
|UART1_TX
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|SECO_UART_TX
+
|SECO.TX
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|SPI2_PCS0
+
|SPI2.PCS0
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|TPM1_CH1
+
|TPM1.CH1
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO1_IO05//BOOT_MODE[0]
+
|GPIO1_IO05
 
|-
 
|-
 
| rowspan="5" |J1.189
 
| rowspan="5" |J1.189
Line 1,603: Line 1,603:
 
| rowspan="5" |CPU.UART1_RXD
 
| rowspan="5" |CPU.UART1_RXD
 
| rowspan="5" |E20
 
| rowspan="5" |E20
−
| rowspan="5" |NVCC_3V3
+
| rowspan="5" |NVCC_GPIO
 
| rowspan="5" |IO
 
| rowspan="5" |IO
−
| rowspan="5" |Used as default Linux console (Cortex-A55)
+
| rowspan="5" |
 
|Pin ALT-0
 
|Pin ALT-0
 
|UART1_RX
 
|UART1_RX
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|SECO_UART_RX
+
|SECO.RX
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|SPI2_SIN
+
|SPI2.SIN
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|TPM1_CH0
+
|TPM1.CH0
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
Line 1,625: Line 1,625:
 
| rowspan="8" |CPU.GPIO_IO12
 
| rowspan="8" |CPU.GPIO_IO12
 
| rowspan="8" |N20
 
| rowspan="8" |N20
−
| rowspan="8" |NVCC_3V3
+
| rowspan="8" |NVCC_GPIO
 
| rowspan="8" |IO
 
| rowspan="8" |IO
 
| rowspan="8" |
 
| rowspan="8" |
Line 1,632: Line 1,632:
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|TPM3_CH2
+
|TPM3.CH2
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|PDM_BIT_STREAM02
+
|PDM.BIT_STREAM[2]
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA08
+
|LCDIF.D[8]
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|SPI8_PCS0
+
|SPI8.PCS0
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|UART8_TX
+
|UART8.TX
 
|-
 
|-
 
|Pin ALT-6
 
|Pin ALT-6
−
|I2C8_SDA
+
|I2C8.SDA
 
|-
 
|-
 
|Pin ALT-7
 
|Pin ALT-7
−
|SAI3_RX_SYNC
+
|SAI3.RX_SYNC
 
|-
 
|-
 
| rowspan="8" |J1.193
 
| rowspan="8" |J1.193
Line 1,656: Line 1,656:
 
| rowspan="8" |CPU.GPIO_IO13
 
| rowspan="8" |CPU.GPIO_IO13
 
| rowspan="8" |N21
 
| rowspan="8" |N21
−
| rowspan="8" |NVCC_3V3
+
| rowspan="8" |NVCC_GPIO
 
| rowspan="8" |IO
 
| rowspan="8" |IO
 
| rowspan="8" |
 
| rowspan="8" |
Line 1,663: Line 1,663:
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|TPM4_CH2
+
|TPM4.CH2
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|PDM_BIT_STREAM03
+
|PDM.BIT_STREAM[3]
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA09
+
|LCDIF.D[9]
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|SPI8_SIN
+
|SPI8.SIN
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|UART8_RX
+
|UART8.RX
 
|-
 
|-
 
|Pin ALT-6
 
|Pin ALT-6
−
|I2C8_SCL
+
|I2C8.SCL
 
|-
 
|-
 
|Pin ALT-7
 
|Pin ALT-7
−
|FLEXIO1_FLEXIO13
+
|FLEXIO1.FLEXIO[13]
 
|-
 
|-
 
| rowspan="8" |J1.195
 
| rowspan="8" |J1.195
Line 1,687: Line 1,687:
 
| rowspan="8" |CPU.GPIO_IO02
 
| rowspan="8" |CPU.GPIO_IO02
 
| rowspan="8" |K21
 
| rowspan="8" |K21
−
| rowspan="8" |NVCC_3V3
+
| rowspan="8" |NVCC_GPIO
 
| rowspan="8" |IO
 
| rowspan="8" |IO
 
| rowspan="8" |
 
| rowspan="8" |
Line 1,694: Line 1,694:
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|I2C4_SDA
+
|I2C4.SDA
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAM_VSYNC
+
|ISI.FRAME_VALID
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_VSYNC
+
|LCDIF.VSYNC
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|SPI6_SOUT
+
|SPI6.SOUT
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|UART5_CTS_B
+
|UART5.CTS_B
 
|-
 
|-
 
|Pin ALT-6
 
|Pin ALT-6
−
|I2C6_SDA
+
|I2C6.SDA
 
|-
 
|-
 
|Pin ALT-7
 
|Pin ALT-7
−
|FLEXIO1_FLEXIO02
+
|FLEXIO1.FLEXIO[2]
 
|-
 
|-
 
|J1.197
 
|J1.197
Line 1,728: Line 1,728:
 
| rowspan="7" |CPU.PDM_BIT_STREAM0
 
| rowspan="7" |CPU.PDM_BIT_STREAM0
 
| rowspan="7" |J17
 
| rowspan="7" |J17
−
| rowspan="7" |NVCC_3V3
+
| rowspan="7" |NVCC_GPIO
 
| rowspan="7" |IO
 
| rowspan="7" |IO
 
| rowspan="7" |
 
| rowspan="7" |
 
|Pin ALT-0
 
|Pin ALT-0
−
|PDM_BIT_STREAM00
+
|PDM_BIT_STREAM0
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|MQS1_RIGHT
+
|MQS1.RIGHT
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|SPI1_PCS1
+
|SPI1.PCS1
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|TPM1_EXTCLK
+
|TPM1.EXTCLK
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|LPTMR1_ALT2
+
|LPTMR1.ALT2
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO1_IO09
+
|GPIO1.IO09
 
|-
 
|-
 
|Pin ALT-6
 
|Pin ALT-6
−
|CAN1_RX
+
|CAN1.RX
 
|-
 
|-
 
| rowspan="5" |J1.201
 
| rowspan="5" |J1.201
Line 1,756: Line 1,756:
 
| rowspan="5" |CPU.PDM_CLK
 
| rowspan="5" |CPU.PDM_CLK
 
| rowspan="5" |G17
 
| rowspan="5" |G17
−
| rowspan="5" |NVCC_3V3
+
| rowspan="5" |NVCC_GPIO
 
| rowspan="5" |IO
 
| rowspan="5" |IO
 
| rowspan="5" |
 
| rowspan="5" |
Line 1,763: Line 1,763:
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|MQS1_LEFT
+
|MQS1.LEFT
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|LPTMR1_ALT1
+
|LPTMR1.ALT1
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO1_IO08
+
|GPIO1.IO08
 
|-
 
|-
 
|Pin ALT-6
 
|Pin ALT-6
−
|CAN1_TX
+
|CAN1.TX
 
|-
 
|-
 
|J1.203
 
|J1.203
Line 1,876: Line 1,876:
 
|
 
|
 
|
 
|
−
|-
+
|}
−
|J1.18
 
−
|SOM_PGOOD
 
−
| -
 
−
| -
 
−
|NVCC_3V3
 
−
|O
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.20
 
−
|BOOT_MODE_SEL
 
−
|BOOT MODE SELECTION
 
−
| -
 
−
|NVCC_3V3
 
−
|I
 
−
|internal pull-up to NVCC_3V3
 
−
|
 
−
|
 
−
|-
 
−
|J1.22
 
−
|CPU_PORn
 
−
|CPU.POR_B
 
−
PMIC.POR_B
 
−
|A16
 
−
9
 
−
|NVCC_BBSM_1V8
 
−
|I/O
 
−
|internal pull-up 100k to NVCC_BBSM_1V8
 
−
|
 
−
|
 
−
|-
 
−
|J1.24
 
−
|PMIC_ON_REQ
 
−
|PMIC.PMIC_ON_REQ
 
−
|39
 
−
|NVCC_BBSM_1V8
 
−
|I
 
−
|internal pull-up 100k to NVCC_BBSM_1V8
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="6" |J1.26
 
−
| rowspan="6" |PDM_BIT_STREAM1
 
−
| rowspan="6" |CPU.PDM_BIT_STREAM1
 
−
| rowspan="6" |JG18
 
−
| rowspan="6" |NVCC_3V3
 
−
| rowspan="6" |IO
 
−
| rowspan="6" |
 
−
|Pin ALT-0
 
−
|PDM_BIT_STREAM01
 
−
|-
 
−
|Pin ALT-1
 
−
|NMI_GLUE_NMI
 
−
|-
 
−
|Pin ALT-2
 
−
|SPI2_PCS1
 
−
|-
 
−
|Pin ALT-3
 
−
|TPM2_EXTCLK
 
−
|-
 
−
|Pin ALT-4
 
−
|LPTMR1_ALT3
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO1_IO10
 
−
|-
 
−
| rowspan="2" |J1.28
 
−
| rowspan="2" |WDOG_ANY
 
−
| rowspan="2" |CPU.PDM_BIT_STREAM1
 
−
| rowspan="2" |JG18
 
−
| rowspan="2" |NVCC_3V3
 
−
| rowspan="2" |IO
 
−
| rowspan="2" |
 
−
|Pin ALT-0
 
−
|WDOG1_WDOG_ANY
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO1_IO15
 
−
|-
 
−
|J1.30
 
−
|DGND
 
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.32
 
−
|PMIC_STBY_REQ
 
−
|PMIC.PMIC_STBY_REQ
 
−
|40
 
−
|NVCC_BBSM_1V8
 
−
|O
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="8" |J1.34
 
−
| rowspan="8" |GPIO_IO17
 
−
| rowspan="8" |CPU.GPIO_IO17
 
−
| rowspan="8" |R20
 
−
| rowspan="8" |NVCC_3V3
 
−
| rowspan="8" |IO
 
−
| rowspan="8" |
 
−
|Pin ALT-0
 
−
|GPIO2_IO17
 
−
|-
 
−
|Pin ALT-1
 
−
|SAI3_MCLK
 
−
|-
 
−
|Pin ALT-2
 
−
|CAM_DATA08
 
−
|-
 
−
|Pin ALT-3
 
−
|DISP_DATA13
 
−
|-
 
−
|Pin ALT-4
 
−
|UART3_RTS_B
 
−
|-
 
−
|Pin ALT-5
 
−
|SPI4_PCS1
 
−
|-
 
−
|Pin ALT-6
 
−
|UART4_RTS_B
 
−
|-
 
−
|Pin ALT-7
 
−
|FLEXIO1_FLEXIO17
 
−
|-
 
−
| rowspan="8" |J1.36
 
−
| rowspan="8" |GPIO_IO21
 
−
| rowspan="8" |CPU.GPIO_IO21
 
−
| rowspan="8" |T21
 
−
| rowspan="8" |NVCC_3V3
 
−
| rowspan="8" |IO
 
−
| rowspan="8" |
 
−
|Pin ALT-0
 
−
|GPIO2_IO21
 
−
|-
 
−
|Pin ALT-1
 
−
|SAI3_TX_DATA00
 
−
|-
 
−
|Pin ALT-2
 
−
|PDM_CLK
 
−
|-
 
−
|Pin ALT-3
 
−
|DISP_DATA17
 
−
|-
 
−
|Pin ALT-4
 
−
|SPI5_SCK
 
−
|-
 
−
|Pin ALT-5
 
−
|SPI4_SCK
 
−
|-
 
−
|Pin ALT-6
 
−
|TPM4_CH1
 
−
|-
 
−
|Pin ALT-7
 
−
|SAI3_RX_BCLK
 
−
|-
 
−
| rowspan="3" |J1.38
 
−
| rowspan="3" |GPIO_IO29
 
−
| rowspan="3" |CPU.GPIO_IO29
 
−
| rowspan="3" |Y21
 
−
| rowspan="3" |NVCC_3V3
 
−
| rowspan="3" |IO
 
−
| rowspan="3" |
 
−
|Pin ALT-0
 
−
|GPIO2_IO29
 
−
|-
 
−
|Pin ALT-1
 
−
|I2C3_SCL
 
−
|-
 
−
|Pin ALT-7
 
−
|FLEXIO1_FLEXIO29
 
−
|-
 
−
| rowspan="8" |J1.40
 
−
| rowspan="8" |GPIO_IO07
 
−
| rowspan="8" |CPU.GPIO_IO07
 
−
| rowspan="8" |L21
 
−
| rowspan="8" |NVCC_3V3
 
−
| rowspan="8" |IO
 
−
| rowspan="8" |
 
−
|Pin ALT-0
 
−
|GPIO2_IO07
 
−
|-
 
−
|Pin ALT-1
 
−
|SPI3_PCS1
 
−
|-
 
−
|Pin ALT-2
 
−
|CAM_DATA01
 
−
|-
 
−
|Pin ALT-3
 
−
|DISP_DATA03
 
−
|-
 
−
|Pin ALT-4
 
−
|SPI7_SCK
 
−
|-
 
−
|Pin ALT-5
 
−
|UART6_RTS_B
 
−
|-
 
−
|Pin ALT-6
 
−
|I2C7_SCL
 
−
|-
 
−
|Pin ALT-7
 
−
|FLEXIO1_FLEXIO07
 
−
|-
 
−
| rowspan="8" |J1.42
 
−
| rowspan="8" |GPIO_IO25//CAN_H
 
−
| rowspan="8" |CPU.GPIO_IO25
 
−
CAN.CANH
 
−
| rowspan="8" |V21
 
−
7
 
−
| rowspan="8" |NVCC_3V3
 
−
| rowspan="8" |IO
 
−
| rowspan="8" |optional CAN transceiver
 
−
|Pin ALT-0
 
−
|GPIO2_IO25
 
−
|-
 
−
|Pin ALT-1
 
−
|USDHC3_DATA1
 
−
|-
 
−
|Pin ALT-2
 
−
|CAN2_TX
 
−
|-
 
−
|Pin ALT-3
 
−
|DISP_DATA21
 
−
|-
 
−
|Pin ALT-4
 
−
|TPM4_CH3
 
−
|-
 
−
|Pin ALT-5
 
−
|JTAG_MUX_TCK
 
−
|-
 
−
|Pin ALT-6
 
−
|SPI7_PCS1
 
−
|-
 
−
|Pin ALT-7
 
−
|FLEXIO1_FLEXIO25
 
−
|-
 
−
| rowspan="8" |J1.44
 
−
| rowspan="8" |GPIO_IO27//CAN_L
 
−
| rowspan="8" |CPU.GPIO_IO27
 
−
CAN.CANL
 
−
| rowspan="8" |W21
 
−
6
 
−
| rowspan="8" |NVCC_3V3
 
−
| rowspan="8" |IO
 
−
| rowspan="8" |optional CAN transceiver
 
−
|Pin ALT-0
 
−
|GPIO2_IO27
 
−
|-
 
−
|Pin ALT-1
 
−
|USDHC3_DATA3
 
−
|-
 
−
|Pin ALT-2
 
−
|CAN2_RX
 
−
|-
 
−
|Pin ALT-3
 
−
|DISP_DATA23
 
−
|-
 
−
|Pin ALT-4
 
−
|TPM6_CH3
 
−
|-
 
−
|Pin ALT-5
 
−
|JTAG_MUX_TMS
 
−
|-
 
−
|Pin ALT-6
 
−
|SPI5_PCS1
 
−
|-
 
−
|Pin ALT-7
 
−
|FLEXIO1_FLEXIO27
 
−
|-
 
−
| rowspan="7" |J1.46
 
−
| rowspan="7" |GPIO_IO24
 
−
| rowspan="7" |CPU.GPIO_IO24
 
−
| rowspan="7" |U21
 
−
| rowspan="7" |NVCC_3V3
 
−
| rowspan="7" |IO
 
−
| rowspan="7" |
 
−
|Pin ALT-0
 
−
|GPIO2_IO24
 
−
|-
 
−
|Pin ALT-1
 
−
|USDHC3_DATA0
 
−
|-
 
−
|Pin ALT-3
 
−
|DISP_DATA20
 
−
|-
 
−
|Pin ALT-4
 
−
|TPM3_CH3
 
−
|-
 
−
|Pin ALT-5
 
−
|JTAG_MUX_TDO
 
−
|-
 
−
|Pin ALT-6
 
−
|SPI6_PSC1
 
−
|-
 
−
|Pin ALT-7
 
−
|FLEXIO1_FLEXIO24
 
−
|-
 
−
| rowspan="3" |J1.48
 
−
| rowspan="3" |GPIO_IO28
 
−
| rowspan="3" |CPU.GPIO_IO28
 
−
| rowspan="3" |W20
 
−
| rowspan="3" |NVCC_3V3
 
−
| rowspan="3" |IO
 
−
| rowspan="3" |
 
−
|Pin ALT-0
 
−
|GPIO2_IO28
 
−
|-
 
−
|Pin ALT-1
 
−
|I2C3_SDA
 
−
|-
 
−
|Pin ALT-7
 
−
|FLEXIO1_FLEXIO28
 
−
|-
 
−
| rowspan="3" |J1.50
 
−
| rowspan="3" |CCM_CLK01
 
−
| rowspan="3" |CPU.CCM_CLK01
 
−
| rowspan="3" |AA2
 
−
| rowspan="3" |NVCC_3V3
 
−
| rowspan="3" |IO
 
−
| rowspan="3" |
 
−
|Pin ALT-0
 
−
|CCMSRCGPCMIX_CLK01
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO1_FLEXIO26
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO3_IO26
 
−
|-
 
−
| rowspan="3" |J1.52
 
−
| rowspan="3" |CCM_CLK02
 
−
| rowspan="3" |CPU.CCM_CLK02
 
−
| rowspan="3" |Y3
 
−
| rowspan="3" |NVCC_3V3
 
−
| rowspan="3" |IO
 
−
| rowspan="3" |
 
−
|Pin ALT-0
 
−
|CCMSRCGPCMIX_CLK02
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO1_FLEXIO27
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO3_IO27
 
−
|-
 
−
| rowspan="3" |J1.54
 
−
| rowspan="3" |CCM_CLK03
 
−
| rowspan="3" |CPU.CCM_CLK03
 
−
| rowspan="3" |U4
 
−
| rowspan="3" |NVCC_3V3
 
−
| rowspan="3" |IO
 
−
| rowspan="3" |
 
−
|Pin ALT-0
 
−
|CCMSRCGPCMIX_CLK01
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO28
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO28
 
−
|-
 
−
|J1.56
 
−
|DGND
 
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.58
 
−
|ETH_RSTn
 
−
|LAN.RESETn
 
−
|43
 
−
|NVCC_3V3
 
−
|I
 
−
|Hardware mounting option
 
−
|
 
−
|
 
−
|-
 
−
|J1.60
 
−
|ETH_INTn
 
−
|LAN.INT_N
 
−
|39
 
−
|NVCC_3V3
 
−
|O
 
−
|Hardware mounting option
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="6" |J1.62
 
−
| rowspan="6" |SAI1_RXD0
 
−
| rowspan="6" |CPU.SAI1_RXD0
 
−
| rowspan="6" |H20
 
−
| rowspan="6" |NVCC_3V3
 
−
| rowspan="6" |IO
 
−
| rowspan="6" |
 
−
|Pin ALT-0
 
−
|SAI1_RX_DATA00
 
−
|-
 
−
|Pin ALT-1
 
−
|SAI1_MCLK
 
−
|-
 
−
|Pin ALT-2
 
−
|SPI1_SOUT
 
−
|-
 
−
|Pin ALT-3
 
−
|UART2_DSR_B
 
−
|-
 
−
|Pin ALT-4
 
−
|MQS1_RIGHT
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO1_IO14
 
−
|-
 
−
| rowspan="3" |J1.64
 
−
| rowspan="3" |CCM_CLK04
 
−
| rowspan="3" |CPU.CCM_CLK04
 
−
| rowspan="3" |V4
 
−
| rowspan="3" |NVCC_3V3
 
−
| rowspan="3" |IO
 
−
| rowspan="3" |
 
−
|Pin ALT-0
 
−
|CCMSRCGPCMIX_CLK04
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO29
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO29
 
−
|-
 
−
| rowspan="8" |J1.66
 
−
| rowspan="8" |GPIO_IO16
 
−
| rowspan="8" |CPU.GPIO_IO16
 
−
| rowspan="8" |R21
 
−
| rowspan="8" |NVCC_3V3
 
−
| rowspan="8" |IO
 
−
| rowspan="8" |
 
−
|Pin ALT-0
 
−
|GPIO2_IO16
 
−
|-
 
−
|Pin ALT-1
 
−
|SAI3_TX_BCLK
 
−
|-
 
−
|Pin ALT-2
 
−
|PDM_BIT_STREAM02
 
−
|-
 
−
|Pin ALT-3
 
−
|DISP_DATA12
 
−
|-
 
−
|Pin ALT-4
 
−
|UART3_CTS_B
 
−
|-
 
−
|Pin ALT-5
 
−
|SPI4_PCS2
 
−
|-
 
−
|Pin ALT-6
 
−
|UART4_CTS_B
 
−
|-
 
−
|Pin ALT-7
 
−
|FLEXIO1_FLEXIO16
 
−
|-
 
−
| rowspan="8" |J1.68
 
−
| rowspan="8" |GPIO_IO19
 
−
| rowspan="8" |CPU.GPIO_IO19
 
−
| rowspan="8" |R17
 
−
| rowspan="8" |NVCC_3V3
 
−
| rowspan="8" |IO
 
−
| rowspan="8" |
 
−
|Pin ALT-0
 
−
|GPIO2_IO19
 
−
|-
 
−
|Pin ALT-1
 
−
|SAI3_RX_SYNC
 
−
|-
 
−
|Pin ALT-2
 
−
|PDM_BIT_STREAM03
 
−
|-
 
−
|Pin ALT-3
 
−
|DISP_DATA15
 
−
|-
 
−
|Pin ALT-4
 
−
|SPI5_SIN
 
−
|-
 
−
|Pin ALT-5
 
−
|SPI4_SIN
 
−
|-
 
−
|Pin ALT-6
 
−
|TPM4_CH2
 
−
|-
 
−
|Pin ALT-7
 
−
|SAI3_TX_DATA00
 
−
|-
 
−
| rowspan="8" |J1.70
 
−
| rowspan="8" |GPIO_IO26
 
−
| rowspan="8" |CPU.GPIO_IO26
 
−
| rowspan="8" |V20
 
−
| rowspan="8" |NVCC_3V3
 
−
| rowspan="8" |IO
 
−
| rowspan="8" |
 
−
|Pin ALT-0
 
−
|GPIO2_IO26
 
−
|-
 
−
|Pin ALT-1
 
−
|USDHC3_DATA2
 
−
|-
 
−
|Pin ALT-2
 
−
|PDM_BIT_STREAM01
 
−
|-
 
−
|Pin ALT-3
 
−
|DISP_DATA22
 
−
|-
 
−
|Pin ALT-4
 
−
|TPM3_CH3
 
−
|-
 
−
|Pin ALT-5
 
−
|JTAG_MUX_TDI
 
−
|-
 
−
|Pin ALT-6
 
−
|SPI8_PCS1
 
−
|-
 
−
|Pin ALT-7
 
−
|SAI3_TX_SYNC
 
−
|-
 
−
| rowspan="8" |J1.72
 
−
| rowspan="8" |GPIO_IO20
 
−
| rowspan="8" |CPU.GPIO_IO20
 
−
| rowspan="8" |T20
 
−
| rowspan="8" |NVCC_3V3
 
−
| rowspan="8" |IO
 
−
| rowspan="8" |
 
−
|Pin ALT-0
 
−
|GPIO2_IO20
 
−
|-
 
−
|Pin ALT-1
 
−
|SAI3_RX_DATA00
 
−
|-
 
−
|Pin ALT-2
 
−
|PDM_BIT_STREAM00
 
−
|-
 
−
|Pin ALT-3
 
−
|DISP_DATA16
 
−
|-
 
−
|Pin ALT-4
 
−
|SPI5_SOUT
 
−
|-
 
−
|Pin ALT-5
 
−
|SPI4_SOUT
 
−
|-
 
−
|Pin ALT-6
 
−
|TPM3_CH1
 
−
|-
 
−
|Pin ALT-7
 
−
|FLEXIO1_FLEXIO20
 
−
|-
 
−
| rowspan="8" |J1.74
 
−
| rowspan="8" |GPIO_IO22
 
−
| rowspan="8" |CPU.GPIO_IO22
 
−
| rowspan="8" |U18
 
−
| rowspan="8" |NVCC_3V3
 
−
| rowspan="8" |IO
 
−
| rowspan="8" |
 
−
|Pin ALT-0
 
−
|GPIO2_IO22
 
−
|-
 
−
|Pin ALT-1
 
−
|USDHC3_CLK
 
−
|-
 
−
|Pin ALT-2
 
−
|SPDIF_IN
 
−
|-
 
−
|Pin ALT-3
 
−
|DISP_DATA18
 
−
|-
 
−
|Pin ALT-4
 
−
|TPM5_CH1
 
−
|-
 
−
|Pin ALT-5
 
−
|TPM6_EXTCLK
 
−
|-
 
−
|Pin ALT-6
 
−
|I2C5_SDA
 
−
|-
 
−
|Pin ALT-7
 
−
|FLEXIO1_FLEXIO22
 
−
|-
 
−
| rowspan="7" |J1.76
 
−
| rowspan="7" |GPIO_IO23
 
−
| rowspan="7" |CPU.GPIO_IO23
 
−
| rowspan="7" |U20
 
−
| rowspan="7" |NVCC_3V3
 
−
| rowspan="7" |IO
 
−
| rowspan="7" |
 
−
|Pin ALT-0
 
−
|GPIO2_IO23
 
−
|-
 
−
|Pin ALT-1
 
−
|USDHC3_CMD
 
−
|-
 
−
|Pin ALT-2
 
−
|SPDIF_OUT
 
−
|-
 
−
|Pin ALT-3
 
−
|DISP_DATA19
 
−
|-
 
−
|Pin ALT-4
 
−
|TPM6_CH1
 
−
|-
 
−
|Pin ALT-6
 
−
|I2C5_SCL
 
−
|-
 
−
|Pin ALT-7
 
−
|FLEXIO1_FLEXIO23
 
−
|-
 
−
| rowspan="8" |J1.78
 
−
| rowspan="8" |GPIO_IO05
 
−
| rowspan="8" |CPU.GPIO_IO05
 
−
| rowspan="8" |L18
 
−
| rowspan="8" |NVCC_3V3
 
−
| rowspan="8" |IO
 
−
| rowspan="8" |
 
−
|Pin ALT-0
 
−
|GPIO2_IO05
 
−
|-
 
−
|Pin ALT-1
 
−
|TPM4_CH0
 
−
|-
 
−
|Pin ALT-2
 
−
|PDM_BIT_STREAM00
 
−
|-
 
−
|Pin ALT-3
 
−
|DISP_DATA01
 
−
|-
 
−
|Pin ALT-4
 
−
|SPI7_SIN
 
−
|-
 
−
|Pin ALT-5
 
−
|UART6_RX
 
−
|-
 
−
|Pin ALT-6
 
−
|I2C6_SCL
 
−
|-
 
−
|Pin ALT-7
 
−
|FLEXIO1_FLEXIO05
 
−
|-
 
−
| rowspan="8" |J1.80
 
−
| rowspan="8" |GPIO_IO04
 
−
| rowspan="8" |CPU.GPIO_IO04
 
−
| rowspan="8" |L17
 
−
| rowspan="8" |NVCC_3V3
 
−
| rowspan="8" |IO
 
−
| rowspan="8" |
 
−
|Pin ALT-0
 
−
|GPIO2_IO04
 
−
|-
 
−
|Pin ALT-1
 
−
|TPM3_CH0
 
−
|-
 
−
|Pin ALT-2
 
−
|PDM_CLK
 
−
|-
 
−
|Pin ALT-3
 
−
|DISP_DATA00
 
−
|-
 
−
|Pin ALT-4
 
−
|SPI7_PCS0
 
−
|-
 
−
|Pin ALT-5
 
−
|UART6_TX
 
−
|-
 
−
|Pin ALT-6
 
−
|I2C6_SDA
 
−
|-
 
−
|Pin ALT-7
 
−
|FLEXIO1_FLEXIO04
 
−
|-
 
−
|J1.82
 
−
|DGND
 
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="1" |J1.84
 
−
| rowspan="1" |TAMPER0
 
−
| rowspan="1" |CPU.TAMPER0
 
−
| rowspan="1" |B16
 
−
| rowspan="1" |NVCC_3V3
 
−
| rowspan="1" |I
 
−
| rowspan="1" |
 
−
|Pin ALT-0
 
−
|BBSMMIX.TAMPER0
 
−
|-
 
−
| rowspan="1" |J1.86
 
−
| rowspan="1" |TAMPER1
 
−
| rowspan="1" |CPU.TAMPER1
 
−
| rowspan="1" |F14
 
−
| rowspan="1" |NVCC_3V3
 
−
| rowspan="1" |I
 
−
| rowspan="1" |
 
−
|Pin ALT-0
 
−
|BBSMMIX.TAMPER1
 
−
|-
 
−
| rowspan="2" |J1.88
 
−
| rowspan="2" |CLKIN1
 
−
| rowspan="2" |CPU.CLKIN1
 
−
| rowspan="2" |B17
 
−
| rowspan="2" |NVCC_3V3
 
−
| rowspan="2" |I
 
−
| rowspan="2" |
 
−
|Pin ALT-0
 
−
|ANAMIX.CLKIN1
 
−
|-
 
−
|Pin ALT-1
 
−
|ANAMIX.ESD_DIODE
 
−
|-
 
−
| rowspan="2" |J1.90
 
−
| rowspan="2" |CLKIN2
 
−
| rowspan="2" |CPU.CLKIN2
 
−
| rowspan="2" |A18
 
−
| rowspan="2" |NVCC_3V3
 
−
| rowspan="2" |I
 
−
| rowspan="2" |
 
−
|Pin ALT-0
 
−
|ANAMIX.CLKIN2
 
−
|-
 
−
|Pin ALT-1
 
−
|ANAMIX.ATX
 
−
|-
 
−
| rowspan="6" |J1.92
 
−
| rowspan="6" |JTAG_TDI
 
−
| rowspan="6" |CPU.DAP_TDI
 
−
| rowspan="6" |W1
 
−
| rowspan="6" |NVCC_3V3
 
−
| rowspan="6" |IO
 
−
| rowspan="6" |
 
−
|Pin ALT-0
 
−
|JTAG_MUX_TDI
 
−
|-
 
−
|Pin ALT-1
 
−
|MQS2_LEFT
 
−
|-
 
−
|Pin ALT-3
 
−
|CAN2_TX
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO30
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO3_IO28
 
−
|-
 
−
|Pin ALT-6
 
−
|UART5_RX
 
−
|-
 
−
| rowspan="4" |J1.94
 
−
| rowspan="4" |JTAG_TMS
 
−
| rowspan="4" |CPU.DAP_TMS_SWDIO
 
−
| rowspan="4" |W2
 
−
| rowspan="4" |NVCC_3V3
 
−
| rowspan="4" |IO
 
−
| rowspan="4" |
 
−
|Pin ALT-0
 
−
|JTAG_MUX_TMS
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO31
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO3_IO29
 
−
|-
 
−
|Pin ALT-6
 
−
|UART5_RTS_B
 
−
|-
 
−
| rowspan="4" |J1.96
 
−
| rowspan="4" |JTAG_TMS
 
−
| rowspan="4" |CPU.DAP_TCLK_SWCLK
 
−
| rowspan="4" |Y1
 
−
| rowspan="4" |NVCC_3V3
 
−
| rowspan="4" |IO
 
−
| rowspan="4" |
 
−
|Pin ALT-0
 
−
|JTAG_MUX_TCK
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO1_FLEXIO30
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO3_IO30
 
−
|-
 
−
|Pin ALT-6
 
−
|UART5_CTS_B
 
−
|-
 
−
| rowspan="6" |J1.98
 
−
| rowspan="6" |JTAG_TDO
 
−
| rowspan="6" |CPU.DAP_TDO_TRACE_SWO
 
−
| rowspan="6" |W1
 
−
| rowspan="6" |NVCC_3V3
 
−
| rowspan="6" |IO
 
−
| rowspan="6" |
 
−
|Pin ALT-0
 
−
|JTAG_MUX_TDO
 
−
|-
 
−
|Pin ALT-1
 
−
|MQS2_RIGHT
 
−
|-
 
−
|Pin ALT-3
 
−
|CAN2_RX
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO1_FLEXIO31
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO3_IO31
 
−
|-
 
−
|Pin ALT-6
 
−
|UART5_TX
 
−
|-
 
−
|J1.100
 
−
|DGND
 
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.102
 
−
|CSI_CLK_N
 
−
|CPU.MIPI_CSI1_CLK_N
 
−
|D10
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.104
 
−
|CSI_CLK_P
 
−
|CPU.MIPI_CSI1_CLK_P
 
−
|E10
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.106
 
−
|CSI_D0_N
 
−
|CPU.MIPI_CSI1_D0_N
 
−
|A11
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.108
 
−
|CSI_D0_P
 
−
|CPU.MIPI_CSI1_D0_P
 
−
|B11
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.110
 
−
|CSI_D1_N
 
−
|CPU.MIPI_CSI1_D1_N
 
−
|A10
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.112
 
−
|CSI_D1_P
 
−
|CPU.MIPI_CSI1_D1_P
 
−
|B10
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.114
 
−
|USB1_RX_N
 
−
|CPU.USB1_RX_N
 
−
|A12
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|Only for i.MX933x/i.MX935x
 
−
|
 
−
|
 
−
|-
 
−
|J1.116
 
−
|USB1_RX_P
 
−
|CPU.USB1_RX_P
 
−
|B12
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|Only for i.MX933x/i.MX935x
 
−
|
 
−
|
 
−
|-
 
−
|J1.118
 
−
|USB1_TX_N
 
−
|CPU.USB1_TX_N
 
−
|A13
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|Only for i.MX933x/i.MX935x
 
−
|
 
−
|
 
−
|-
 
−
|J1.120
 
−
|USB1_TX_P
 
−
|CPU.USB1_TX_P
 
−
|B13
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|Only for i.MX933x/i.MX935x
 
−
|
 
−
|
 
−
|-
 
−
|J1.122
 
−
|DGND
 
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="6" |J1.124
 
−
| rowspan="6" |ENET1_MDC
 
−
| rowspan="6" |CPU.ENET1_MDC
 
−
| rowspan="6" |AA11
 
−
| rowspan="6" |NVCC_3V3
 
−
| rowspan="6" |IO
 
−
| rowspan="6" |
 
−
|Pin ALT-0
 
−
|ENET_QOS_MDC
 
−
|-
 
−
|Pin ALT-1
 
−
|UART3_DCR_B
 
−
|-
 
−
|Pin ALT-2
 
−
|I3C2_SCL
 
−
|-
 
−
|Pin ALT-3
 
−
|USB1_OTG_ID
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO00
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO00
 
−
|-
 
−
| rowspan="6" |J1.126
 
−
| rowspan="6" |ENET1_MDIO
 
−
| rowspan="6" |CPU.ENET1_MDIO
 
−
| rowspan="6" |AA10
 
−
| rowspan="6" |NVCC_3V3
 
−
| rowspan="6" |IO
 
−
| rowspan="6" |
 
−
|Pin ALT-0
 
−
|ENET_QOS_MDIO
 
−
|-
 
−
|Pin ALT-1
 
−
|UART3_RIN_B
 
−
|-
 
−
|Pin ALT-2
 
−
|I3C2_SDA
 
−
|-
 
−
|Pin ALT-3
 
−
|USB1_OTG_PWR
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO01
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO01
 
−
|-
 
−
| rowspan="3" |J1.128
 
−
| rowspan="3" |SD1_CLK
 
−
| rowspan="3" |CPU.SD1_CLK
 
−
| rowspan="3" |Y11
 
−
| rowspan="3" |NVCC_3V3
 
−
| rowspan="3" |IO
 
−
| rowspan="3" |
 
−
|Pin ALT-0
 
−
|USDHC1_CLK
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO1_FLEXIO08
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO3_IO08
 
−
|-
 
−
| rowspan="3" |J1.130
 
−
| rowspan="3" |SD1_CMD
 
−
| rowspan="3" |CPU.SD1_CMD
 
−
| rowspan="3" |AA12
 
−
| rowspan="3" |NVCC_3V3
 
−
| rowspan="3" |IO
 
−
| rowspan="3" |
 
−
|Pin ALT-0
 
−
|USDHC1_CMD
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO1_FLEXIO09
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO3_IO09
 
−
|-
 
−
|J1.132
 
−
|ETH1_LED5
 
−
|LAN.LED5/GPIO4
 
−
|13
 
−
|NVCC_3V3
 
−
|O
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="4" |J1.134
 
−
| rowspan="4" |SD1_STROBE
 
−
| rowspan="4" |CPU.SD1_CLK
 
−
| rowspan="4" |Y11
 
−
| rowspan="4" |NVCC_3V3
 
−
| rowspan="4" |IO
 
−
| rowspan="4" |
 
−
|Pin ALT-0
 
−
|USDHC1_CLK
 
−
|-
 
−
|Pin ALT-1
 
−
|FLEXSPI1_A_DQS
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO1_FLEXIO18
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO3_IO018
 
−
|-
 
−
|J1.136
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="3" |J1.138
 
−
| rowspan="3" |SD1_DATA0
 
−
| rowspan="3" |CPU.SD1_DATA0
 
−
| rowspan="3" |AA14
 
−
| rowspan="3" |NVCC_3V3
 
−
| rowspan="3" |IO
 
−
| rowspan="3" |
 
−
|Pin ALT-0
 
−
|USDHC1_DATA0
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO1_FLEXIO10
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO3_IO10
 
−
|-
 
−
| rowspan="3" |J1.140
 
−
| rowspan="3" |SD1_DATA1
 
−
| rowspan="3" |CPU.SD1_DATA1
 
−
| rowspan="3" |AA15
 
−
| rowspan="3" |NVCC_3V3
 
−
| rowspan="3" |IO
 
−
| rowspan="3" |
 
−
|Pin ALT-0
 
−
|USDHC1_DATA1
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO1_FLEXIO11
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO3_IO11
 
−
|-
 
−
| rowspan="3" |J1.142
 
−
| rowspan="3" |SD1_DATA2
 
−
| rowspan="3" |CPU.SD1_DATA2
 
−
| rowspan="3" |AA16
 
−
| rowspan="3" |NVCC_3V3
 
−
| rowspan="3" |IO
 
−
| rowspan="3" |
 
−
|Pin ALT-0
 
−
|USDHC1_DATA2
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO1_FLEXIO12
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO3_IO12
 
−
|-
 
−
| rowspan="3" |J1.144
 
−
| rowspan="3" |SD1_DATA3
 
−
| rowspan="3" |CPU.SD1_DATA3
 
−
| rowspan="3" |Y11
 
−
| rowspan="3" |NVCC_3V3
 
−
| rowspan="3" |IO
 
−
| rowspan="3" |
 
−
|Pin ALT-0
 
−
|USDHC1_DATA3
 
−
|-
 
−
|Pin ALT-1
 
−
|FLEXSPI1_A_SS1_B
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO1_FLEXIO13
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO3_IO13
 
−
|-
 
−
|J1.146
 
−
|DGND
 
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="4" |J1.148
 
−
| rowspan="4" |SD1_DATA4
 
−
| rowspan="4" |CPU.SD1_DATA4
 
−
| rowspan="4" |Y13
 
−
| rowspan="4" |NVCC_3V3
 
−
| rowspan="4" |IO
 
−
| rowspan="4" |
 
−
|Pin ALT-0
 
−
|USDHC1_DATA4
 
−
|-
 
−
|Pin ALT-1
 
−
|FLEXSPI1_A_DATA04
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO1_FLEXIO14
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO3_IO14
 
−
|-
 
−
| rowspan="4" |J1.150
 
−
| rowspan="4" |SD1_DATA5
 
−
| rowspan="4" |CPU.SD1_DATA5
 
−
| rowspan="4" |Y14
 
−
| rowspan="4" |NVCC_3V3
 
−
| rowspan="4" |IO
 
−
| rowspan="4" |
 
−
|Pin ALT-0
 
−
|USDHC1_DATA5
 
−
|-
 
−
|Pin ALT-1
 
−
|FLEXSPI1_A_DATA05
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO1_FLEXIO15
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO3_IO15
 
−
|-
 
−
| rowspan="4" |J1.152
 
−
| rowspan="4" |SD1_DATA5
 
−
| rowspan="4" |CPU.SD1_DATA6
 
−
| rowspan="4" |Y15
 
−
| rowspan="4" |NVCC_3V3
 
−
| rowspan="4" |IO
 
−
| rowspan="4" |
 
−
|Pin ALT-0
 
−
|USDHC1_DATA6
 
−
|-
 
−
|Pin ALT-1
 
−
|FLEXSPI1_A_DATA06
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO1_FLEXIO16
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO3_IO16
 
−
|-
 
−
| rowspan="4" |J1.154
 
−
| rowspan="4" |SD1_DATA7
 
−
| rowspan="4" |CPU.SD1_DATA7
 
−
| rowspan="4" |Y16
 
−
| rowspan="4" |NVCC_3V3
 
−
| rowspan="4" |IO
 
−
| rowspan="4" |
 
−
|Pin ALT-0
 
−
|USDHC1_DATA7
 
−
|-
 
−
|Pin ALT-1
 
−
|FLEXSPI1_A_DATA07
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO1_FLEXIO17
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO3_IO17
 
−
|-
 
−
| rowspan="4" |J1.156
 
−
| rowspan="4" |ENET2_TD3
 
−
| rowspan="4" |CPU.ENET2_TD3
 
−
| rowspan="4" |T10
 
−
| rowspan="4" |NVCC_3V3
 
−
| rowspan="4" |IO
 
−
| rowspan="4" |
 
−
|Pin ALT-0
 
−
|ENET1_RGMII_TD3
 
−
|-
 
−
|Pin ALT-2
 
−
|SAI2_RX_DATA00
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO16
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO16
 
−
|-
 
−
| rowspan="5" |J1.158
 
−
| rowspan="5" |ENET2_TD2
 
−
| rowspan="5" |CPU.ENET2_TD2
 
−
| rowspan="5" |V8
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |IO
 
−
| rowspan="5" |
 
−
|Pin ALT-0
 
−
|ENET1_RGMII_TD2
 
−
|-
 
−
|Pin ALT-1
 
−
|ENET1_TX_CLK // CCMSRCGPMCMIX.ENET_REF_CLK_ROOT
 
−
|-
 
−
|Pin ALT-2
 
−
|SAI2_RX_DATA01
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO17
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO17
 
−
|-
 
−
| rowspan="5" |J1.160
 
−
| rowspan="5" |ENET2_TD1
 
−
| rowspan="5" |CPU.ENET2_TD1
 
−
| rowspan="5" |U8
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |IO
 
−
| rowspan="5" |
 
−
|Pin ALT-0
 
−
|ENET1_RGMII_TD1
 
−
|-
 
−
|Pin ALT-1
 
−
|UART4_RTS_B
 
−
|-
 
−
|Pin ALT-2
 
−
|SAI2_RX_DATA02
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO18
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO18
 
−
|-
 
−
| rowspan="5" |J1.162
 
−
| rowspan="5" |ENET2_TD0
 
−
| rowspan="5" |CPU.ENET2_TD0
 
−
| rowspan="5" |T8
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |IO
 
−
| rowspan="5" |
 
−
|Pin ALT-0
 
−
|ENET1_RGMII_TD0
 
−
|-
 
−
|Pin ALT-1
 
−
|UART4_TX
 
−
|-
 
−
|Pin ALT-2
 
−
|SAI2_RX_DATA03
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO19
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO19
 
−
|-
 
−
|J1.164
 
−
|DGND
 
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="5" |J1.166
 
−
| rowspan="5" |ENET2_TXC
 
−
| rowspan="5" |CPU.ENET2_TXC
 
−
| rowspan="5" |U6
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |IO
 
−
| rowspan="5" |
 
−
|Pin ALT-0
 
−
|ENET1_RGMI_TXC
 
−
|-
 
−
|Pin ALT-1
 
−
|ENET1_TX_ER
 
−
|-
 
−
|Pin ALT-2
 
−
|SAI2_TX_BCLK
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO21
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO21
 
−
|-
 
−
| rowspan="5" |J1.168
 
−
| rowspan="5" |ENET2_TX_CTL
 
−
| rowspan="5" |CPU.ENET2_TX_CTL
 
−
| rowspan="5" |V6
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |IO
 
−
| rowspan="5" |
 
−
|Pin ALT-0
 
−
|ENET1_RGMI_TX_CTL
 
−
|-
 
−
|Pin ALT-1
 
−
|UART4_DTR_B
 
−
|-
 
−
|Pin ALT-2
 
−
|SAI2_TX_SYNC
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO20
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO20
 
−
|-
 
−
| rowspan="5" |J1.170
 
−
| rowspan="5" |ENET2_MDC
 
−
| rowspan="5" |CPU.ENET2_MDC
 
−
| rowspan="5" |Y7
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |IO
 
−
| rowspan="5" |
 
−
|Pin ALT-0
 
−
|ENET1_MDC
 
−
|-
 
−
|Pin ALT-1
 
−
|UART4_DCR_B
 
−
|-
 
−
|Pin ALT-2
 
−
|SAI2_RX_SYNC
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO14
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO14
 
−
|-
 
−
| rowspan="5" |J1.172
 
−
| rowspan="5" |ENET2_MDIO
 
−
| rowspan="5" |CPU.ENET2_MDIO
 
−
| rowspan="5" |AA6
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |IO
 
−
| rowspan="5" |
 
−
|Pin ALT-0
 
−
|ENET1_MDIO
 
−
|-
 
−
|Pin ALT-1
 
−
|UART4_RIN_B
 
−
|-
 
−
|Pin ALT-2
 
−
|SAI2_RX_BCLK
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO15
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO15
 
−
|-
 
−
| rowspan="5" |J1.174
 
−
| rowspan="5" |ENET2_RX_CTL
 
−
| rowspan="5" |CPU.ENET2_RX_CTL
 
−
| rowspan="5" |Y4
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |IO
 
−
| rowspan="5" |
 
−
|Pin ALT-0
 
−
|ENET1_RGMII_RX_CTL
 
−
|-
 
−
|Pin ALT-1
 
−
|UART4_DSR_B
 
−
|-
 
−
|Pin ALT-2
 
−
|SAI2_TX_DATA00
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO22
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO22
 
−
|-
 
−
| rowspan="5" |J1.176
 
−
| rowspan="5" |ENET2_RD0
 
−
| rowspan="5" |CPU.ENET2_RD0
 
−
| rowspan="5" |AA4
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |IO
 
−
| rowspan="5" |
 
−
|Pin ALT-0
 
−
|ENET1_RGMII_RD0
 
−
|-
 
−
|Pin ALT-1
 
−
|UART4_RX
 
−
|-
 
−
|Pin ALT-2
 
−
|SAI2_TX_DATA02
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO24
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO24
 
−
|-
 
−
| rowspan="5" |J1.178
 
−
| rowspan="5" |ENET2_RD1
 
−
| rowspan="5" |CPU.ENET2_RD1
 
−
| rowspan="5" |Y5
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |IO
 
−
| rowspan="5" |
 
−
|Pin ALT-0
 
−
|ENET1_RGMII_RD1
 
−
|-
 
−
|Pin ALT-1
 
−
|SPDIF_IN
 
−
|-
 
−
|Pin ALT-2
 
−
|SAI2_TX_DATA03
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO25
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO25
 
−
|-
 
−
| rowspan="6" |J1.180
 
−
| rowspan="6" |ENET2_RD2
 
−
| rowspan="6" |CPU.ENET2_RD2
 
−
| rowspan="6" |AA5
 
−
| rowspan="6" |NVCC_3V3
 
−
| rowspan="6" |IO
 
−
| rowspan="6" |
 
−
|Pin ALT-0
 
−
|ENET1_RGMII_RD2
 
−
|-
 
−
|Pin ALT-1
 
−
|UART4_CTS_B
 
−
|-
 
−
|Pin ALT-2
 
−
|SAI2_MCLK
 
−
|-
 
−
|Pin ALT-3
 
−
|MQS2_RIGHT
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO26
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO26
 
−
|-
 
−
| rowspan="6" |J1.182
 
−
| rowspan="6" |ENET2_RD3
 
−
| rowspan="6" |CPU.ENET2_RD3
 
−
| rowspan="6" |Y6
 
−
| rowspan="6" |NVCC_3V3
 
−
| rowspan="6" |IO
 
−
| rowspan="6" |
 
−
|Pin ALT-0
 
−
|ENET1_RGMII_RD3
 
−
|-
 
−
|Pin ALT-1
 
−
|SPDIF_OUT
 
−
|-
 
−
|Pin ALT-2
 
−
|SPDIF_IN
 
−
|-
 
−
|Pin ALT-3
 
−
|MQS2_LEFT
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO27
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO27
 
−
|-
 
−
| rowspan="5" |J1.184
 
−
| rowspan="5" |ENET2_RXC
 
−
| rowspan="5" |CPU.ENET2_RXC
 
−
| rowspan="5" |AA3
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |IO
 
−
| rowspan="5" |
 
−
|Pin ALT-0
 
−
|ENET1_RGMII_RXC
 
−
|-
 
−
|Pin ALT-1
 
−
|ENET1_RX_ER
 
−
|-
 
−
|Pin ALT-2
 
−
|SAI2_TX_DATA01
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO23
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO23
 
−
|-
 
−
|J1.186
 
−
|USB1_VBUS
 
−
|CPU.USB1_VBUS
 
−
|F13
 
−
|NVCC_3V3
 
−
|D
 
−
|(3V3 reference signal)
 
−
|
 
−
|
 
−
|-
 
−
|J1.188
 
−
|USB2_VBUS
 
−
|CPU.USB2_VBUS
 
−
|E14
 
−
|NVCC_3V3
 
−
|D
 
−
|(3V3 reference signal)
 
−
|
 
−
|
 
−
|-
 
−
|J1.190
 
−
|DGND
 
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.192
 
−
|USB1_ID
 
−
|CPU.USB1_ID
 
−
|C11
 
−
|
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.194
 
−
|USB2_ID
 
−
|CPU.USB2_ID
 
−
|E12
 
−
|
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.196
 
−
|USB1_DN
 
−
|CPU.USB1_DN
 
−
|A14
 
−
|
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.198
 
−
|USB1_DP
 
−
|CPU.USB1_DP
 
−
|B14
 
−
|
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.200
 
−
|USB2_DP
 
−
|CPU.USB2_DP
 
−
|B15
 
−
|
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.202
 
−
|USB2_DN
 
−
|CPU.USB2_DN
 
−
|A15
 
−
|
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.204
 
−
|DGND
 
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
−
|}
 
−
 
 
 
----
 
----
  
 
[[Category:AURA]]
 
[[Category:AURA]]

Revision as of 08:09, 16 May 2023

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History
ID# Issue Date Notes

17891

15/05/2023 Preliminary version


Connectors and Pinout Table[edit | edit source]

Connectors description[edit | edit source]

In the following table are described all available connectors integrated on AURA SOM:

Connector name Connector Type Notes Carrier board counterpart
J1 SODIMM DDR3 edge connector 204 pin TE Connectivity 2013289-1

The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to AURA pinout specifications. See the images below for reference:

AURA TOP view
AURA BOTTOM view

Pinout table naming conventions[edit | edit source]

This chapter contains the pinout description of the AURA module, grouped in two tables (odd and even pins) that report the pin mapping of the 204-pin SO-DIMM AURA connector.

Each row in the pinout tables contains the following information:

Pin Reference to the connector pin
Pin Name Pin (signal) name on the AURA connectors
Internal
connections 		Connections to the AURA components
  • CPU.<x> : pin connected to CPU pad named <x>
  • CAN.<x> : pin connected to the CAN transceiver (TI SN65HVD232)
  • PMIC.<x> : pin connected to the Power Manager IC (NXP PCA9451A)
  • LAN.<x> : pin connected to the LAN PHY (Microchip LAN8830T-V)
  • NOR.<x>: pin connected to the flash NOR
  • SV.<x>: pin connected to voltage supervisor
  • MTR: pin connected to voltage monitors
Ball/pin # Component ball/pin number connected to signal
Voltage I/O voltage levels
Type Pin type:
  • I = Input
  • O = Output
  • D = Differential
  • Z = High impedance
  • S = Power supply voltage
  • G = Ground
  • A = Analog signal
Notes Remarks on special pin characteristics
Pin MUX alternative functions Muxes:
  • Pin ALT-0
  • ...
  • Pin ALT-N

The number of functions depends on platform

Voltage domains[edit | edit source]

Voltage domain Nominal voltage [V] Notes
3.3VIN 3.3 See Operational_characteristics of the SoM wiki page
NVCC_3V3 3.3 Voltage generated by the internal PSU. See Power Supply Unit (PSU) wiki page
NVCC_GPIO 3.3 Voltage generated by the internal PSU. See Power Supply Unit (PSU) wiki page
VDD_ANA_1V8 1.8

Pinout Table ODD pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage

domain

Type Notes Alternative Functions
J1.1 DGND DGND - - G
J1.3 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.5 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.7 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.9 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.11 DGND DGND - - G
J1.13 ETH1_LED1 LAN.LED1/GPIO0 18 NVCC_3V3 O
J1.15 ETH1_LED2 LAN.LED2/GPIO1 16 NVCC_3V3 O
J1.17 DGND DGND - - G
J1.19 ETH1_TXRX0_P LAN.TXRXP_A 2 NVCC_3V3 D
J1.21 ETH1_TXRX0_M LAN.TXRXM_A 3 NVCC_3V3 D
J1.23 ETH1_TXRX1_P LAN.TXRXP_B 5 NVCC_3V3 D
J1.25 ETH1_TXRX1_M LAN.TXRXM_B 6 NVCC_3V3 D
J1.27 ETH1_TXRX2_P LAN.TXRXP_C 7 NVCC_3V3 D
J1.29 ETH1_TXRX2_M LAN.TXRXM_C 8 NVCC_3V3 D
J1.31 ETH1_TXRX3_P LAN.TXRXP_D 10 NVCC_3V3 D
J1.33 ETH1_TXRX3_M LAN.TXRXM_D 11 NVCC_3V3 D
J1.35 DGND DGND - - G
J1.37 ETH1_LED3 LAN.LED3/GPIO2 15 NVCC_3V3 O
J1.39 ETH1_LED4 LAN.LED4/GPIO3 14 NVCC_3V3 O
J1.41 ETH_OSC_EN 46 NVCC_3V3 I (mounting option)
J1.43 GPIO_IO06 CPU.GPIO_IO06 L20 NVCC_GPIO IO Pin ALT-0 GPIO2_IO06
Pin ALT-1 TMP5.CH0
Pin ALT-2 PDM.BIT_STREAM[1]
Pin ALT-3 LCDIF.D[2]
Pin ALT-4 SPI7.SOUT
Pin ALT-5 UART6.CTS_B
Pin ALT-6 I2C7.SDA
Pin ALT-7 FLEXIO1.FLEXIO[6]
J1.45 GPIO_IO18 CPU.GPIO_IO18 R18 NVCC_GPIO IO Pin ALT-0 GPIO2_IO18
Pin ALT-1 SAI3.RX_BCLK
Pin ALT-2 ISI.D[9]
Pin ALT-3 LCDIF.D[14]
Pin ALT-4 SPI5.PCS0
Pin ALT-5 SPI4.PCS0
Pin ALT-6 TMP5.CH2
Pin ALT-7 FLEXIO1.FLEXIO[18]
J1.47 GPIO_IO09 CPU.GPIO_IO09 M21 NVCC_GPIO IO Pin ALT-0 GPIO2_IO09
Pin ALT-1 SPI3.SIN
Pin ALT-2 ISI.D[3]
Pin ALT-3 LCDIF.D[5]
Pin ALT-4 TMP3.EXTCLK
Pin ALT-5 UART7.RX
Pin ALT-6 I2C7.SCL
Pin ALT-7 FLEXIO1.FLEXIO[9]
J1.49 GPIO_IO08 CPU.GPIO_IO08 M20 NVCC_GPIO IO Pin ALT-0 GPIO2_IO08
Pin ALT-1 SPI3.SPCS0
Pin ALT-2 ISI.D[2]
Pin ALT-3 LCDIF.D[4]
Pin ALT-4 TMP6.CH0
Pin ALT-5 UART7.TX
Pin ALT-6 I2C7.SDA
Pin ALT-7 FLEXIO1.FLEXIO[8]
J1.51
J1.53 SAI1_TXFS CPU.SAI1_TXFS//BOOT2 G21 NVCC_AON IO Pin ALT-0 SAI1.TX_SYNC
Pin ALT-1 SAI1.TX_DATA[1]
Pin ALT-2 SPI1.PCS0
Pin ALT-3 UART2_DTR_B
Pin ALT-4 MQS1.LEFT
Pin ALT-5 GPIO1_IO11
Pin ALT-6 BOOT_MODE[2]
J1.55 GPIO_IO10 CPU.GPIO_IO10 N17 NVCC_GPIO IO Pin ALT-0 GPIO2_IO10
Pin ALT-1 SPI3.SOUT
Pin ALT-2 ISI.D[4]
Pin ALT-3 LCDIF.D[6]
Pin ALT-4 TMP4.EXTCLK
Pin ALT-5 UART7.CTS_B
Pin ALT-6 I2C8.SDA
Pin ALT-7 FLEXIO1.FLEXIO[10]
J1.57 DGND DGND - - G
J1.59 GPIO_IO11 CPU.GPIO_IO11 N18 NVCC_GPIO IO Pin ALT-0 GPIO2_IO10
Pin ALT-1 SPI3.SCLK
Pin ALT-2 ISI.D[5]
Pin ALT-3 LCDIF.D[7]
Pin ALT-4 TMP5.EXTCLK
Pin ALT-5 UART7.RTS_B
Pin ALT-6 I2C8.SCL
Pin ALT-7 FLEXIO1.FLEXIO[11]
J1.61 SD3_DATA0 CPU.GPIO_IO11 T16 NVCC_GPIO IO Pin ALT-0 USDHC3.DATA0
Pin ALT-1 FLE_SPI.A_DATA[0]
Pin ALT-4 FLEXIO1.FLEXIO[22]
Pin ALT-5 GPIO3_IO22
J1.63 SD3_DATA1 CPU.GPIO_IO11 V14 NVCC_GPIO IO Pin ALT-0 USDHC3.DATA1
Pin ALT-1 FLE_SPI.A_DATA[1]
Pin ALT-4 FLEXIO1.FLEXIO[23]
Pin ALT-5 GPIO3_IO23
J1.65 SD3_DATA2 CPU.GPIO_IO12 U14 NVCC_GPIO IO Pin ALT-0 USDHC3.DATA2
Pin ALT-1 FLE_SPI.A_DATA[2]
Pin ALT-4 FLEXIO1.FLEXIO[24]
Pin ALT-5 GPIO3_IO24
J1.67 SD3_DATA3 CPU.GPIO_IO13 T14 NVCC_GPIO IO Pin ALT-0 USDHC3.DATA3
Pin ALT-1 FLE_SPI.A_DATA[3]
Pin ALT-4 FLEXIO1.FLEXIO[25]
Pin ALT-5 GPIO3_IO25
J1.69 SD3_CMD CPU.GPIO_IO21 U16 NVCC_GPIO IO Pin ALT-0 USDHC3.CMD
Pin ALT-1 FLE_SPI.A_SS0_B
Pin ALT-4 FLEXIO1.FLEXIO[21]
Pin ALT-5 GPIO3_IO21
J1.71 SD3_CLK CPU.GPIO_IO20 V16 NVCC_GPIO IO Pin ALT-0 USDHC3.CLK
Pin ALT-1 FLE_SPI.A_SCLK
Pin ALT-4 FLEXIO1.FLEXIO[20]
Pin ALT-5 GPIO3_IO20
J1.73 DGND DGND - - G
J1.75 SD2_DATA0 CPU.SD2_DATA0 Y18 NVCC_GPIO IO Pin ALT-0 USDHC2.DATA0
Pin ALT-1 ENET2.1588_EVENT0_OUT
Pin ALT-2 CAN2.TX
Pin ALT-4 FLEXIO1.FLEXIO[3]
Pin ALT-5 GPIO3_IO03
J1.77 SD2_DATA1 CPU.SD2_DATA1 AA18 NVCC_GPIO IO Pin ALT-0 USDHC2.DATA1
Pin ALT-1 ENET2.1588_EVENT1_IN
Pin ALT-2 CAN2.RX
Pin ALT-4 FLEXIO1.FLEXIO[4]
Pin ALT-5 GPIO3_IO04
J1.79 SD2_DATA2 CPU.SD2_DATA2 Y20 NVCC_GPIO IO Pin ALT-0 USDHC2.DATA2
Pin ALT-1 ENET2.1588_EVENT1_OUT
Pin ALT-2 MQS1.RIGHT
Pin ALT-4 FLEXIO1.FLEXIO[5]
Pin ALT-5 GPIO3_IO05
J1.81 SD2_DATA3 CPU.SD2_DATA3 AA20 NVCC_GPIO IO Pin ALT-0 USDHC2.DATA3
Pin ALT-1 LPTMR2.ALT1
Pin ALT-2 MQS1.LEFT
Pin ALT-4 FLEXIO1.FLEXIO[6]
Pin ALT-5 GPIO3_IO06
J1.83 SD2_CMD CPU.SD2_CMD Y19 NVCC_GPIO IO Pin ALT-0 USDHC2.CMD
Pin ALT-1 ENET2.1588_EVENT0_IN
Pin ALT-2 I3C2.PUR
Pin ALT-3 I3C2.PUR_B
Pin ALT-4 FLEXIO1.FLEXIO[2]
Pin ALT-5 GPIO3_IO02
J1.85 SD2_CLK CPU.SD2_CLK AA19 NVCC_GPIO IO Pin ALT-0 USDHC2.CLK
Pin ALT-1 ENET_QOS.1588_EVENT0_OUT
Pin ALT-2 I3C2.SDA
Pin ALT-4 FLEXIO1.FLEXIO[1]
Pin ALT-5 GPIO3_IO01
J1.87 DGND DGND - - G
J1.89 GPIO_IO14 CPU.GPIO_IO14 P20 NVCC_GPIO IO Pin ALT-0 GPIO2_IO14
Pin ALT-1 UART3.TX
Pin ALT-2 ISI.D[6]
Pin ALT-3 LCDIF.D[10]
Pin ALT-4 SPI8.SOUT
Pin ALT-5 UART8.CTS_B
Pin ALT-6 UART4.TX
Pin ALT-7 FLEXIO1.FLEXIO[14]
J1.91 GPIO_IO15 CPU.GPIO_IO15 P21 NVCC_GPIO IO Pin ALT-0 GPIO2_IO15
Pin ALT-1 UART3.RX
Pin ALT-2 ISI.D[7]
Pin ALT-3 LCDIF.D[11]
Pin ALT-4 SPI8.SCK
Pin ALT-5 UART8.RTS_B
Pin ALT-6 UART4.RX
Pin ALT-7 FLEXIO1.FLEXIO[15]
J1.93 UART2_TXD CPU.UART2_TXD//BOOT1 F21 NVCC_GPIO IO Pin ALT-0 UART2_TX
Pin ALT-1 UART1.RTS_B
Pin ALT-2 SPI2.SCK
Pin ALT-3 TMP1.CH3
Pin ALT-5 GPIO1_IO07//BOOT_MODE[1]
J1.95 UART2_RXD CPU.UART2_RXD F20 NVCC_GPIO IO Pin ALT-0 UART2_RX
Pin ALT-1 UART1.CTS_B
Pin ALT-2 SPI2.SOUT
Pin ALT-3 TMP1.CH2
Pin ALT-4 SAI1.MCLK
Pin ALT-5 GPIO1_IO06
J1.97 SD2_VSELECT CPU.SD2_VSELECT V18 NVCC_GPIO IO Pin ALT-0 USDHC2.VSELECT
Pin ALT-1 USHDC2.WP
Pin ALT-2 LPTMR2.ALT3
Pin ALT-4 FLEXIO1.FLEXIO[19]
Pin ALT-5 GPIO3_IO19
J1.99 SD2_RESET_B CPU.SD2_RESET_B AA17 NVCC_GPIO IO Pin ALT-0 USDHC2.RESET_B
Pin ALT-1 LPTMR2.ALT2
Pin ALT-4 FLEXIO1.FLEXIO[7]
Pin ALT-5 GPIO3_IO07
J1.101 I2C1_SCL CPU.I2C1_SCL C20 NVCC_GPIO IO Pin ALT-0 I2C1.SCL
Pin ALT-1 I3C1.SCL
Pin ALT-2 UART1.DCB_B
Pin ALT-3 TMP2.CH0
Pin ALT-5 GPIO1_IO00
J1.103 I2C1_SDA CPU.I2C1_SDA C21 NVCC_GPIO IO Pin ALT-0 I2C1.SDA
Pin ALT-1 I3C1.SDA
Pin ALT-2 UART1.RIN_B
Pin ALT-3 TMP2.CH1
Pin ALT-5 GPIO1_IO01
J1.105 SAI1_TXD0 CPU.SAI1_TXD0//BOOT3 H21 NVCC_GPIO IO Pin ALT-0 SAI1.TX_DATA[0]
Pin ALT-1 UART2.RTS_B
Pin ALT-2 SPI1.SCK
Pin ALT-3 UART1.DTR_B
Pin ALT-4 CAN1.TX
Pin ALT-5 GPIO1_IO13//BOOT_MODE[3]
J1.107 SAI1_TXC CPU.SAI1_TXC G20 NVCC_GPIO IO Pin ALT-0 SAI1.TX_BCLK
Pin ALT-1 UART2.CTS_B
Pin ALT-2 SPI1.SIN
Pin ALT-3 UART1.DSR_B
Pin ALT-4 CAN1.RX
Pin ALT-5 GPIO1_IO12
J1.109 DGND DGND - - G
J1.111 ADC_IN0 CPU.ADC_IN0 B19 NVCC_GPIO IO Pin ALT-0 ANAMIX.ADC_IN0
J1.113 ADC_IN1 CPU.ADC_IN1 A20 NVCC_GPIO IO Pin ALT-0 ANAMIX.ADC_IN1
J1.115 ADC_IN2 CPU.ADC_IN2 B20 NVCC_GPIO IO Pin ALT-0 ANAMIX.ADC_IN2
J1.117 ADC_IN3 CPU.ADC_IN3 B21 NVCC_GPIO IO Pin ALT-0 ANAMIX.ADC_IN3
J1.119 PMIC_SCLH PMIC.SCLH 25 -
J1.121 PMIC_SDAH PMIC.SDAH 24 -
J1.123 PMIC_SCLL PMIC.SCLL 27 -
J1.125 PMIC_SDAL PMIC.SDAL 26 -
J1.127 I2C2_SDA CPU.I2C2_SDA
PMIC.SDA 		D21
42 		NVCC_GPIO IO Pin ALT-0 I2C2.SDA
Pin ALT-3 UART2.RIN_B
Pin ALT-4 TMP2.CH3
Pin ALT-5 SAI1.RX_BCLK
Pin ALT-5 GPIO1_IO03
J1.129 I2C2_SCL CPU.I2C2_SCL
PMIC.SCL 		D20
41 		NVCC_GPIO IO Pin ALT-0 I2C2.SCL
Pin ALT-1 I3C1.PUR
Pin ALT-3 UART2.DCB_B
Pin ALT-4 TMP2.CH2
Pin ALT-5 SAI1.RX_SYNC
Pin ALT-5 GPIO1_IO02
Pin ALT-6 I3C1.PUR_B
J1.131 DGND DGND - - G
J1.133 LVDS_CLK_N CPU.LVDS_CLK_N A3 VDD_ANA_1V8 D
J1.135 LVDS_CLK_P CPU.LVDS_CLK_P B3 VDD_ANA_1V8 D
J1.137 LVDS_TX0_N CPU.LVDS_TX0_N A5 VDD_ANA_1V8 D
J1.139 LVDS_TX0_P CPU.LVDS_TX0_P B5 VDD_ANA_1V8 D
J1.141 LVDS_TX1_N CPU.LVDS_TX1_N A4 VDD_ANA_1V8 D
J1.143 LVDS_TX1_P CPU.LVDS_TX1_P B4 VDD_ANA_1V8 D
J1.145 LVDS_TX2_N CPU.LVDS_TX2_N A2 VDD_ANA_1V8 D
J1.147 LVDS_TX2_P CPU.LVDS_TX2_P B2 VDD_ANA_1V8 D
J1.149 LVDS_TX3_N CPU.LVDS_TX3_N B1 VDD_ANA_1V8 D
J1.151 LVDS_TX3_P CPU.LVDS_TX3_P C1 VDD_ANA_1V8 D
J1.153 DGND DGND - - G
J1.155 DSI_CLK_N CPU.DSI_CLK_N D6 VDD_ANA_1V8 D
J1.157 DSI_CLK_P CPU.DSI_CLK_P E6 VDD_ANA_1V8 D
J1.159 DSI_TX0_N CPU.DSI_TX0_N A6 VDD_ANA_1V8 D
J1.161 DSI_TX0_P CPU.DSI_TX0_P B6 VDD_ANA_1V8 D
J1.163 DSI_TX1_N CPU.DSI_TX1_N A7 VDD_ANA_1V8 D
J1.165 DSI_TX1_P CPU.DSI_TX1_P B7 VDD_ANA_1V8 D
J1.167 DSI_TX2_N CPU.DSI_TX2_N A8 VDD_ANA_1V8 D
J1.169 DSI_TX2_P CPU.DSI_TX2_P B8 VDD_ANA_1V8 D
J1.171 DSI_TX3_N CPU.DSI_TX3_N A9 VDD_ANA_1V8 D
J1.173 DSI_TX3_P CPU.DSI_TX3_P B9 VDD_ANA_1V8 D
J1.175 DGND DGND - - G
J1.177 SD2_CD_B CPU.GPIO_IO08 M20 NVCC_GPIO IO Pin ALT-0 USDHC2.CD_B
Pin ALT-1 ENET_QOS.1588_EVENT0_IN
Pin ALT-2 I2C3.SCL
Pin ALT-4 FLEXIO1.FLEXIO[0]
Pin ALT-5 GPIO3_IO00
J1.179 GPIO_IO00 CPU.GPIO_IO00 J21 NVCC_GPIO IO Pin ALT-0 GPIO2_IO00
Pin ALT-1 I2C3.SDA
Pin ALT-2 ISI.PCLK
Pin ALT-3 LCDIF.PCLK
Pin ALT-4 SPI6.PCS0
Pin ALT-5 UART5.TX
Pin ALT-6 I2C5.SDA
Pin ALT-7 FLEXIO1.FLEXIO[0]
J1.181 GPIO_IO03 CPU.GPIO_IO03 K21 NVCC_GPIO IO Pin ALT-0 GPIO2_IO03
Pin ALT-1 I2C4.SCL
Pin ALT-2 ISI.LINE_VALID
Pin ALT-3 LCDIF.HSYNC
Pin ALT-4 SPI6.SCK
Pin ALT-5 UART5.RTS_B
Pin ALT-6 I2C6.SCL
Pin ALT-7 FLEXIO1.FLEXIO[3]
J1.183 GPIO_IO01 CPU.GPIO_IO01 K21 NVCC_GPIO IO Pin ALT-0 GPIO2_IO01
Pin ALT-1 I2C3.SCL
Pin ALT-2 ISI.D[0]
Pin ALT-3 LCDIF.DE
Pin ALT-4 SPI6.SIN
Pin ALT-5 UART5.RX
Pin ALT-6 I2C5.SCL
Pin ALT-7 FLEXIO1.FLEXIO[1]
J1.185 - - - -
J1.187 UART1_TXD CPU.UART1_TXD//BOOT_MODE0 E21 NVCC_GPIO IO Pin ALT-0 UART1_TX
Pin ALT-1 SECO.TX
Pin ALT-2 SPI2.PCS0
Pin ALT-3 TPM1.CH1
Pin ALT-5 GPIO1_IO05
J1.189 UART1_RXD CPU.UART1_RXD E20 NVCC_GPIO IO Pin ALT-0 UART1_RX
Pin ALT-1 SECO.RX
Pin ALT-2 SPI2.SIN
Pin ALT-3 TPM1.CH0
Pin ALT-5 GPIO1_IO04
J1.191 GPIO_IO12 CPU.GPIO_IO12 N20 NVCC_GPIO IO Pin ALT-0 GPIO2_IO12
Pin ALT-1 TPM3.CH2
Pin ALT-2 PDM.BIT_STREAM[2]
Pin ALT-3 LCDIF.D[8]
Pin ALT-4 SPI8.PCS0
Pin ALT-5 UART8.TX
Pin ALT-6 I2C8.SDA
Pin ALT-7 SAI3.RX_SYNC
J1.193 GPIO_IO13 CPU.GPIO_IO13 N21 NVCC_GPIO IO Pin ALT-0 GPIO2_IO13
Pin ALT-1 TPM4.CH2
Pin ALT-2 PDM.BIT_STREAM[3]
Pin ALT-3 LCDIF.D[9]
Pin ALT-4 SPI8.SIN
Pin ALT-5 UART8.RX
Pin ALT-6 I2C8.SCL
Pin ALT-7 FLEXIO1.FLEXIO[13]
J1.195 GPIO_IO02 CPU.GPIO_IO02 K21 NVCC_GPIO IO Pin ALT-0 GPIO2_IO13
Pin ALT-1 I2C4.SDA
Pin ALT-2 ISI.FRAME_VALID
Pin ALT-3 LCDIF.VSYNC
Pin ALT-4 SPI6.SOUT
Pin ALT-5 UART5.CTS_B
Pin ALT-6 I2C6.SDA
Pin ALT-7 FLEXIO1.FLEXIO[2]
J1.197 - - - -
J1.199 PDM_BIT_STREAM0 CPU.PDM_BIT_STREAM0 J17 NVCC_GPIO IO Pin ALT-0 PDM_BIT_STREAM0
Pin ALT-1 MQS1.RIGHT
Pin ALT-2 SPI1.PCS1
Pin ALT-3 TPM1.EXTCLK
Pin ALT-4 LPTMR1.ALT2
Pin ALT-5 GPIO1.IO09
Pin ALT-6 CAN1.RX
J1.201 PDM_CLK CPU.PDM_CLK G17 NVCC_GPIO IO Pin ALT-0 PDM_CLK
Pin ALT-1 MQS1.LEFT
Pin ALT-4 LPTMR1.ALT1
Pin ALT-5 GPIO1.IO08
Pin ALT-6 CAN1.TX
J1.203 DGND DGND - - G

Pinout Table EVEN pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage

domain

Type Notes Alternative Functions
J1.2 DGND DGND - - G
J1.4 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.6 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.8 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.10 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.12 DGND DGND - - G
J1.14 SYS_NRST PMIC.PMIC_RST_B 8 I
J1.16 CPU_ON_OFF CPU.ON_OFF A19 NVCC_3V3 I
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