Difference between revisions of "AURA SOM/AURA Hardware/Pinout Table"

From DAVE Developer's Wiki
Jump to: navigation, search
(→‎Pinout Table ODD pins declaration)
(29 intermediate revisions by 2 users not shown)
Line 1: Line 1:
−
<section begin="History" />
+
<section begin=History/>
 
{| style="border-collapse:collapse; "
 
{| style="border-collapse:collapse; "
−
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
+
!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
 
|-  
 
|-  
−
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
+
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|ID#
−
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
+
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date
 +
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes
 
|-
 
|-
−
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |{{oldid|18728|2023/05/15}}
+
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|{{oldid|17891|17891}}
−
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Preliminary version
+
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|15/05/2023
−
|-
+
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Preliminary version
−
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |{{oldid|18879|2023/10/23}}
 
−
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Final SOM release
 
−
|-
 
−
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |{{oldid|18983|2023/12/01}}
 
−
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Pinmux label fix
 
−
|-
 
−
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |2023/12/20
 
−
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |Pin labels renaming<br>Add pinmux spreadsheet download
 
 
|-
 
|-
 
|}
 
|}
−
<section end="History" />
+
<section end=History/>
−
<section begin="Body" />
+
<section begin=Body/>
  
 
==Connectors and Pinout Table==
 
==Connectors and Pinout Table==
Line 38: Line 31:
 
|TE Connectivity 2013289-1
 
|TE Connectivity 2013289-1
 
|}
 
|}
−
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to AURA pinout specifications. See the images below for reference:
+
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to ORCA pinout specifications. See the images below for reference:
  
−
[[File:AURA-SOM_top-pin1-203.png|500px|thumb|AURA TOP view|none]]
+
[[File:AURA-top-pin1-203.png|500px|thumb|AURA TOP view|none]]
−
[[File:AURA-SOM_bottom-pin2-204.png|500px|thumb|AURA BOTTOM view|none]]
+
[[File:AURA-bottom-pin2-204.png|500px|thumb|AURA BOTTOM view|none]]
  
 
===Pinout table naming conventions ===
 
===Pinout table naming conventions ===
  
−
This chapter contains the pinout description of the AURA module, grouped in two tables (odd and even pins) that report the pin mapping of the 204-pin SO-DIMM AURA connector.
+
This chapter contains the pinout description of the AURA module, grouped in two tables (odd and even pins) that report the pin mapping of the ''TBD: connector type'' AURA connector.
  
 
Each row in the pinout tables contains the following information:
 
Each row in the pinout tables contains the following information:
  
−
{| class="wikitable" style="width:50%;"
+
{|class="wikitable" style="width:50%;"
 
|-
 
|-
 
|'''Pin'''
 
|'''Pin'''
Line 63: Line 56:
 
* PMIC.<x> : pin connected to the Power Manager IC (NXP PCA9451A)
 
* PMIC.<x> : pin connected to the Power Manager IC (NXP PCA9451A)
 
* LAN.<x> : pin connected to the LAN PHY (Microchip LAN8830T-V)
 
* LAN.<x> : pin connected to the LAN PHY (Microchip LAN8830T-V)
 +
* NOR.<x>: pin connected to the flash NOR
 +
* SV.<x>: pin connected to voltage supervisor
 +
* MTR: pin connected to voltage monitors
 
|-
 
|-
 
|'''Ball/pin #'''  
 
|'''Ball/pin #'''  
Line 100: Line 96:
 
|3.3VIN
 
|3.3VIN
 
|3.3
 
|3.3
−
|See [[AURA_SOM/AURA_Hardware/Electrical_Thermal_and_Mechanical_Features/Operational_characteristics#Recommended_ratings|Operational_characteristics]] of the SoM wiki page
+
|See [[AURA_SOM/AXEL_Lite_Hardware/Electrical_Thermal_and_Mechanical_Features/Operational_characteristics#Recommended_ratings|Operational_characteristics]] of the SoM wiki page
 
|-
 
|-
−
|NVCC_3V3
+
|VCC_ENET_1V8
 +
|1.8
 +
|Voltage generated by the internal PSU. See [[AURA_SOM/AXEL_Lite_Hardware/Power_and_Reset/Power_Supply_Unit_(PSU)_and_recommended_power-up_sequence | Power Supply Unit (PSU)]] wiki page
 +
|-
 +
|IO_3V3
 
|3.3
 
|3.3
−
|Voltage generated by the internal PSU. See [[AURA_SOM/AURA_Hardware/Power_and_Reset/Power_Supply_Unit_(PSU)_and_recommended_power-up_sequence | Power Supply Unit (PSU)]] wiki page
+
|Voltage generated by the internal PSU. See [[AURA_SOM/AXEL_Lite_Hardware/Power_and_Reset/Power_Supply_Unit_(PSU)_and_recommended_power-up_sequence | Power Supply Unit (PSU)]] wiki page
 
|-
 
|-
−
|VDD_ANA_1V8
+
|GEN_2V5
−
|1.8
+
|2.5
−
|
+
|Voltage generated by the internal PSU. See [[AURA_SOM/AXEL_Lite_Hardware/Power_and_Reset/Power_Supply_Unit_(PSU)_and_recommended_power-up_sequence | Power Supply Unit (PSU)]] wiki page
 
|-
 
|-
 
|}
 
|}
−
 
−
===Pinout table XLS file ===
 
−
For your convenience, please find a spreadsheet with the AURA/MIMX935x pinout and pinmux table [https://www.dave.eu/links/p/hdTvHz4xQ811bdtb here].
 
  
 
==Pinout Table ODD pins declaration ==
 
==Pinout Table ODD pins declaration ==
Line 126: Line 123:
 
! latexfontsize="scriptsize" | Type  
 
! latexfontsize="scriptsize" | Type  
 
! latexfontsize="scriptsize" | Notes
 
! latexfontsize="scriptsize" | Notes
−
! colspan="2" latexfontsize="scriptsize" | Alternative Functions
+
! colspan="2" latexfontsize="scriptsize"| Alternative Functions
 
|-
 
|-
 
|J1.1
 
|J1.1
Line 190: Line 187:
 
|J1.13
 
|J1.13
 
|ETH1_LED1
 
|ETH1_LED1
−
|LAN.LED1/GPIO0
+
|LAN.LED1/PME_N1
 
|18
 
|18
 
|NVCC_3V3
 
|NVCC_3V3
Line 200: Line 197:
 
|J1.15
 
|J1.15
 
|ETH1_LED2
 
|ETH1_LED2
−
|LAN.LED2/GPIO1
+
|LAN.LED2
 
|16
 
|16
 
|NVCC_3V3
 
|NVCC_3V3
Line 334: Line 331:
 
|NVCC_3V3
 
|NVCC_3V3
 
|I
 
|I
−
|mounting option
 
 
|
 
|
 
|
 
|
 +
|(mounting option)
 
|-
 
|-
 
| rowspan="8" |J1.43
 
| rowspan="8" |J1.43
Line 342: Line 339:
 
| rowspan="8" |CPU.GPIO_IO06
 
| rowspan="8" |CPU.GPIO_IO06
 
| rowspan="8" |L20
 
| rowspan="8" |L20
−
| rowspan="8" |NVCC_3V3
+
| rowspan="8" |NVCC_GPIO
 
| rowspan="8" |IO
 
| rowspan="8" |IO
 
| rowspan="8" |
 
| rowspan="8" |
Line 349: Line 346:
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|TPM5_CH0
+
|TMP5_CH0
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|PDM_BIT_STREAM01
+
|PDM.BIT_STREAM[1]
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA02
+
|LCDIF.D[2]
 
|-
 
|-
 
|Pin ALT-4
 
|Pin ALT-4
−
|SPI7_SOUT
+
|SPI7.SOUT
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|UART6_CTS_B
+
|UART6.CTS_B
 
|-
 
|-
 
|Pin ALT-6
 
|Pin ALT-6
−
|I2C7_SDA
+
|I2C7.SDA
 
|-
 
|-
 
|Pin ALT-7
 
|Pin ALT-7
−
|FLEXIO1_FLEXIO06
+
|FLEXIO1.FLEXIO[6]
 +
|}
 +
 
 +
==Pinout Table EVEN  pins declaration ==
 +
 
 +
{| class="wikitable"
 +
! latexfontsize="scriptsize"| Pin
 +
! latexfontsize="scriptsize"| Pin Name
 +
! latexfontsize="scriptsize"| Internal Connections
 +
! latexfontsize="scriptsize"| Ball/pin #
 +
! latexfontsize="scriptsize"| Voltage domain
 +
! latexfontsize="scriptsize"| Type
 +
! latexfontsize="scriptsize"| Notes
 +
! colspan="2" latexfontsize="scriptsize"| Alternative Functions
 
|-
 
|-
−
| rowspan="8" |J1.45
+
|rowspan="5"|J1.2
−
| rowspan="8" |GPIO_IO18
+
|rowspan="5"|SD2_CMD
−
| rowspan="8" |CPU.GPIO_IO18
+
|rowspan="5"|CPU.SD2_CMD
−
| rowspan="8" |R18
+
|rowspan="5"|F19
−
| rowspan="8" |NVCC_3V3
+
|rowspan="5"|AXEL_IO_3V3
−
| rowspan="8" |IO
+
|rowspan="5"|IO
−
| rowspan="8" |
+
|rowspan="5"|Notes
 
|Pin ALT-0
 
|Pin ALT-0
−
|GPIO2_IO18
+
|SD2_CMD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|SAI3_RX_BCLK
+
|ECSPI5_MOSI
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAM_DATA09
+
|KEY_ROW5
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA14
+
|AUD4_RXC
−
|-
 
−
|Pin ALT-4
 
−
|SPI5_PCS0
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|SPI4_PCS0
+
|GPIO1_IO11
−
|-
 
−
|Pin ALT-6
 
−
|TPM5_CH2
 
−
|-
 
−
|Pin ALT-7
 
−
|FLEXIO1_FLEXIO18
 
 
|-
 
|-
−
| rowspan="8" |J1.47
+
|rowspan="5"|J1.4
−
| rowspan="8" |GPIO_IO09
+
|rowspan="5"|TBD
−
| rowspan="8" |CPU.GPIO_IO09
+
|rowspan="5"|TBD
−
| rowspan="8" |M21
+
|rowspan="5"|TBD
−
| rowspan="8" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="8" |IO
+
|rowspan="5"|TBD
−
| rowspan="8" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|GPIO2_IO09
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|SPI3_SIN
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAM_DATA03
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA05
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|TPM3_EXTCLK
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|UART7_RX
+
|TBD
 
|-
 
|-
−
|Pin ALT-6
+
|rowspan="5"|J1.6
−
|I2C7_SCL
+
|rowspan="5"|TBD
−
|-
+
|rowspan="5"|TBD
−
|Pin ALT-7
+
|rowspan="5"|TBD
−
|FLEXIO1_FLEXIO09
+
|rowspan="5"|TBD
−
|-
+
|rowspan="5"|TBD
−
| rowspan="8" |J1.49
+
|rowspan="5"|TBD
−
| rowspan="8" |GPIO_IO08
+
|Pin ALT-0
−
| rowspan="8" |CPU.GPIO_IO08
+
|TBD
−
| rowspan="8" |M20
 
−
| rowspan="8" |NVCC_3V3
 
−
| rowspan="8" |IO
 
−
| rowspan="8" |
 
−
|Pin ALT-0
 
−
|GPIO2_IO08
 
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|SPI3_SPCS0
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAM_DATA02
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA04
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|TPM6_CH0
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|UART7_TX
+
|TBD
−
|-
 
−
|Pin ALT-6
 
−
|I2C7_SDA
 
−
|-
 
−
|Pin ALT-7
 
−
|FLEXIO1_FLEXIO08
 
−
|-
 
−
|J1.51
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="6" |J1.53
+
|rowspan="5"|J1.8
−
| rowspan="6" |SAI1_TXFS
+
|rowspan="5"|TBD
−
| rowspan="6" |CPU.SAI1_TXFS//BOOT2
+
|rowspan="5"|TBD
−
| rowspan="6" |G21
+
|rowspan="5"|TBD
−
| rowspan="6" |NVCC_AON
+
|rowspan="5"|TBD
−
| rowspan="6" |IO
+
|rowspan="5"|TBD
−
| rowspan="6" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|SAI1_TX_SYNC
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|SAI1_TX_DATA01
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|SPI1_PCS0
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|UART2_DTR_B
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|MQS1_LEFT
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO1_IO11//BOOT_MODE[2]
+
|TBD
 
|-
 
|-
−
| rowspan="8" |J1.55
+
|rowspan="5"|J1.10
−
| rowspan="8" |GPIO_IO10
+
|rowspan="5"|TBD
−
| rowspan="8" |CPU.GPIO_IO10
+
|rowspan="5"|TBD
−
| rowspan="8" |N17
+
|rowspan="5"|TBD
−
| rowspan="8" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="8" |IO
+
|rowspan="5"|TBD
−
| rowspan="8" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|GPIO2_IO10
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|SPI3_SOUT
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAM_DATA04
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA06
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|TPM4_EXTCLK
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|UART7_CTS_B
+
|TBD
 
|-
 
|-
−
|Pin ALT-6
+
|rowspan="5"|J1.12
−
|I2C8_SDA
+
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|Pin ALT-7
+
|Pin ALT-3
−
|FLEXIO1_FLEXIO10
+
|TBD
 
|-
 
|-
−
|J1.57
+
|Pin ALT-5
−
|DGND
+
|TBD
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="8" |J1.59
+
|rowspan="5"|J1.14
−
| rowspan="8" |GPIO_IO11
+
|rowspan="5"|TBD
−
| rowspan="8" |CPU.GPIO_IO11
+
|rowspan="5"|TBD
−
| rowspan="8" |N18
+
|rowspan="5"|TBD
−
| rowspan="8" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="8" |IO
+
|rowspan="5"|TBD
−
| rowspan="8" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|GPIO2_IO11
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|SPI3_SCLK
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAM_DATA05
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA07
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|TPM5_EXTCLK
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|UART7_RTS_B
+
|TBD
−
|-
 
−
|Pin ALT-6
 
−
|I2C8_SCL
 
−
|-
 
−
|Pin ALT-7
 
−
|FLEXIO1_FLEXIO11
 
 
|-
 
|-
−
| rowspan="4" |J1.61
+
|rowspan="5"|J1.16
−
| rowspan="4" |SD3_DATA0
+
|rowspan="5"|TBD
−
| rowspan="4" |CPU.GPIO_IO11
+
|rowspan="5"|TBD
−
| rowspan="4" |T16
+
|rowspan="5"|TBD
−
| rowspan="4" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="4" |IO
+
|rowspan="5"|TBD
−
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC3_DATA0
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|FLEXSPI1_A_DATA00
+
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-2
−
|FLEXIO1_FLEXIO22
+
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO3_IO22
+
|TBD
 
|-
 
|-
−
| rowspan="4" |J1.63
+
|rowspan="5"|J1.18
−
| rowspan="4" |SD3_DATA1
+
|rowspan="5"|TBD
−
| rowspan="4" |CPU.GPIO_IO11
+
|rowspan="5"|TBD
−
| rowspan="4" |V14
+
|rowspan="5"|TBD
−
| rowspan="4" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="4" |IO
+
|rowspan="5"|TBD
−
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC3_DATA1
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|FLEXSPI1_A_DATA01
+
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-2
−
|FLEXIO1_FLEXIO23
+
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO3_IO23
+
|TBD
 
|-
 
|-
−
| rowspan="4" |J1.65
+
|rowspan="5"|J1.20
−
| rowspan="4" |SD3_DATA2
+
|rowspan="5"|TBD
−
| rowspan="4" |CPU.GPIO_IO12
+
|rowspan="5"|TBD
−
| rowspan="4" |U14
+
|rowspan="5"|TBD
−
| rowspan="4" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="4" |IO
+
|rowspan="5"|TBD
−
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC3_DATA2
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|FLEXSPI1_A_DATA02
+
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-2
−
|FLEXIO1_FLEXIO24
+
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO3_IO24
+
|TBD
 
|-
 
|-
−
| rowspan="4" |J1.67
+
|rowspan="5"|J1.22
−
| rowspan="4" |SD3_DATA3
+
|rowspan="5"|TBD
−
| rowspan="4" |CPU.GPIO_IO13
+
|rowspan="5"|TBD
−
| rowspan="4" |T14
+
|rowspan="5"|TBD
−
| rowspan="4" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="4" |IO
+
|rowspan="5"|TBD
−
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC3_DATA3
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|FLEXSPI1_A_DATA03
+
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-3
−
|FLEXIO1_FLEXIO25
+
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO3_IO25
+
|TBD
 
|-
 
|-
−
| rowspan="4" |J1.69
+
|rowspan="5"|J1.24
−
| rowspan="4" |SD3_CMD
+
|rowspan="5"|TBD
−
| rowspan="4" |CPU.GPIO_IO21
+
|rowspan="5"|TBD
−
| rowspan="4" |U16
+
|rowspan="5"|TBD
−
| rowspan="4" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="4" |IO
+
|rowspan="5"|TBD
−
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC3_CMD
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|FLEXSPI1_A_SS0_B
+
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-3
−
|FLEXIO1_FLEXIO21
+
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO3_IO21
+
|TBD
 
|-
 
|-
−
| rowspan="4" |J1.71
+
|rowspan="5"|J1.26
−
| rowspan="4" |SD3_CLK
+
|rowspan="5"|TBD
−
| rowspan="4" |CPU.GPIO_IO20
+
|rowspan="5"|TBD
−
| rowspan="4" |V16
+
|rowspan="5"|TBD
−
| rowspan="4" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="4" |IO
+
|rowspan="5"|TBD
−
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC3_CLK
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|FLEXSPI1_A_SCLK
+
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-3
−
|FLEXIO1_FLEXIO20
+
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO3_IO20
+
|TBD
 +
|-
 +
|rowspan="5"|J1.28
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J1.73
+
|Pin ALT-2
−
|DGND
+
|TBD
−
|DGND
+
|-
−
| -
+
|Pin ALT-3
−
| -
+
|TBD
−
|G
+
|-
−
|
+
|Pin ALT-5
−
|
+
|TBD
−
|
 
 
|-
 
|-
−
| rowspan="5" |J1.75
+
|rowspan="5"|J1.30
−
| rowspan="5" |SD2_DATA0
+
|rowspan="5"|TBD
−
| rowspan="5" |CPU.SD2_DATA0
+
|rowspan="5"|TBD
−
| rowspan="5" |Y18
+
|rowspan="5"|TBD
−
| rowspan="5" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="5" |IO
+
|rowspan="5"|TBD
−
| rowspan="5" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC2_DATA0
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|ENET1_1588_EVENT0_OUT
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAN2_TX
+
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-3
−
|FLEXIO1_FLEXIO03
+
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO3_IO03
+
|TBD
 
|-
 
|-
−
| rowspan="5" |J1.77
+
|rowspan="5"|J1.32
−
| rowspan="5" |SD2_DATA1
+
|rowspan="5"|TBD
−
| rowspan="5" |CPU.SD2_DATA1
+
|rowspan="5"|TBD
−
| rowspan="5" |AA18
+
|rowspan="5"|TBD
−
| rowspan="5" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="5" |IO
+
|rowspan="5"|TBD
−
| rowspan="5" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC2_DATA1
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|ENET1_1588_EVENT1_IN
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAN2_RX
+
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-3
−
|FLEXIO1_FLEXIO04
+
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO3_IO04
+
|TBD
 
|-
 
|-
−
| rowspan="5" |J1.79
+
|rowspan="5"|J1.34
−
| rowspan="5" |SD2_DATA2
+
|rowspan="5"|TBD
−
| rowspan="5" |CPU.SD2_DATA2
+
|rowspan="5"|TBD
−
| rowspan="5" |Y20
+
|rowspan="5"|TBD
−
| rowspan="5" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="5" |IO
+
|rowspan="5"|TBD
−
| rowspan="5" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC2_DATA2
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|ENET1_1588_EVENT1_OUT
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|MQS1_RIGHT
+
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-3
−
|FLEXIO1_FLEXIO05
+
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO3_IO05
+
|TBD
 
|-
 
|-
−
| rowspan="5" |J1.81
+
|rowspan="5"|J1.36
−
| rowspan="5" |SD2_DATA3
+
|rowspan="5"|TBD
−
| rowspan="5" |CPU.SD2_DATA3
+
|rowspan="5"|TBD
−
| rowspan="5" |AA20
+
|rowspan="5"|TBD
−
| rowspan="5" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="5" |IO
+
|rowspan="5"|TBD
−
| rowspan="5" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC2_DATA3
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|LPTMR2_ALT1
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|MQS1_LEFT
+
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-3
−
|FLEXIO1_FLEXIO06
+
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO3_IO06
+
|TBD
 
|-
 
|-
−
| rowspan="6" |J1.83
+
|rowspan="5"|J1.38
−
| rowspan="6" |SD2_CMD
+
|rowspan="5"|TBD
−
| rowspan="6" |CPU.SD2_CMD
+
|rowspan="5"|TBD
−
| rowspan="6" |Y19
+
|rowspan="5"|TBD
−
| rowspan="6" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="6" |IO
+
|rowspan="5"|TBD
−
| rowspan="6" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC2_CMD
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|ENET1_1588_EVENT0_IN
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|I3C2_PUR
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|I3C2_PUR_B
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO1_FLEXIO02
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO3_IO02
+
|TBD
 
|-
 
|-
−
| rowspan="5" |J1.85
+
|rowspan="5"|J1.40
−
| rowspan="5" |SD2_CLK
+
|rowspan="5"|TBD
−
| rowspan="5" |CPU.SD2_CLK
+
|rowspan="5"|TBD
−
| rowspan="5" |AA19
+
|rowspan="5"|TBD
−
| rowspan="5" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="5" |IO
+
|rowspan="5"|TBD
−
| rowspan="5" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC2_CLK
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|ENET_QOS_1588_EVENT0_OUT
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|I3C2_SDA
+
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-3
−
|FLEXIO1_FLEXIO01
+
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO3_IO01
+
|TBD
 +
|-
 +
|rowspan="5"|J1.42
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J1.87
+
|Pin ALT-2
−
|DGND
+
|TBD
−
|DGND
+
|-
−
| -
+
|Pin ALT-3
−
| -
+
|TBD
−
|G
+
|-
−
|
+
|Pin ALT-5
−
|
+
|TBD
−
|
 
 
|-
 
|-
−
| rowspan="8" |J1.89
+
|rowspan="5"|J1.44
−
| rowspan="8" |GPIO_IO14
+
|rowspan="5"|TBD
−
| rowspan="8" |CPU.GPIO_IO14
+
|rowspan="5"|TBD
−
| rowspan="8" |P20
+
|rowspan="5"|TBD
−
| rowspan="8" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="8" |IO
+
|rowspan="5"|TBD
−
| rowspan="8" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|GPIO2_IO14
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|UART3_TX
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAM_DATA06
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA10
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|SPI8_SOUT
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|UART8_CTS_B
+
|TBD
−
|-
 
−
|Pin ALT-6
 
−
|UART4_TX
 
−
|-
 
−
|Pin ALT-7
 
−
|FLEXIO1_FLEXIO14
 
 
|-
 
|-
−
| rowspan="8" |J1.91
+
|rowspan="5"|J1.46
−
| rowspan="8" |GPIO_IO15
+
|rowspan="5"|TBD
−
| rowspan="8" |CPU.GPIO_IO15
+
|rowspan="5"|TBD
−
| rowspan="8" |P21
+
|rowspan="5"|TBD
−
| rowspan="8" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="8" |IO
+
|rowspan="5"|TBD
−
| rowspan="8" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|GPIO2_IO15
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|UART3_RX
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAM_DATA07
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA11
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|SPI8_SCK
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|UART8_RTS_B
+
|TBD
−
|-
 
−
|Pin ALT-6
 
−
|UART4_RX
 
 
|-
 
|-
−
|Pin ALT-7
+
|rowspan="5"|J1.48
−
|FLEXIO1_FLEXIO15
+
|rowspan="5"|TBD
−
|-
+
|rowspan="5"|TBD
−
| rowspan="5" |J1.93
+
|rowspan="5"|TBD
−
| rowspan="5" |UART2_TXD
+
|rowspan="5"|TBD
−
| rowspan="5" |CPU.UART2_TXD//BOOT1
+
|rowspan="5"|TBD
−
| rowspan="5" |F21
+
|rowspan="5"|TBD
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |IO
 
−
| rowspan="5" |Used as default console for Cortex-M33
 
 
|Pin ALT-0
 
|Pin ALT-0
−
|UART2_TX
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|UART1_RTS_B
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|SPI2_SCK
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|TPM1_CH3
+
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO1_IO07//BOOT_MODE[1]
+
|TBD
 
|-
 
|-
−
| rowspan="6" |J1.95
+
|rowspan="5"|J1.50
−
| rowspan="6" |UART2_RXD
+
|rowspan="5"|TBD
−
| rowspan="6" |CPU.UART2_RXD
+
|rowspan="5"|TBD
−
| rowspan="6" |F20
+
|rowspan="5"|TBD
−
| rowspan="6" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="6" |IO
+
|rowspan="5"|TBD
−
| rowspan="6" |Used as default console for Cortex-M33
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|UART2_RX
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|UART1_CTS_B
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|SPI2_SOUT
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|TPM1_CH2
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|SAI1_MCLK
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO1_IO06
+
|TBD
 
|-
 
|-
−
| rowspan="5" |J1.97
+
|rowspan="5"|J1.52
−
| rowspan="5" |SD2_VSELECT
+
|rowspan="5"|TBD
−
| rowspan="5" |CPU.SD2_VSELECT
+
|rowspan="5"|TBD
−
| rowspan="5" |V18
+
|rowspan="5"|TBD
−
| rowspan="5" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="5" |IO
+
|rowspan="5"|TBD
−
| rowspan="5" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC2_VSELECT
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|USHDC2_WP
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|LPTMR2_ALT3
+
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-3
−
|FLEXIO1_FLEXIO19
+
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO3_IO19
+
|TBD
 
|-
 
|-
−
| rowspan="4" |J1.99
+
|rowspan="5"|J1.54
−
| rowspan="4" |SD2_RESET_B
+
|rowspan="5"|TBD
−
| rowspan="4" |CPU.SD2_RESET_B
+
|rowspan="5"|TBD
−
| rowspan="4" |AA17
+
|rowspan="5"|TBD
−
| rowspan="4" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="4" |IO
+
|rowspan="5"|TBD
−
| rowspan="4" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC2_RESET_B
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|LPTMR2_ALT2
+
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-3
−
|FLEXIO1_FLEXIO07
+
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO3_IO07
+
|TBD
 
|-
 
|-
−
| rowspan="5" |J1.101
+
|rowspan="5"|J1.56
−
| rowspan="5" |I2C1_SCL
+
|rowspan="5"|TBD
−
| rowspan="5" |CPU.I2C1_SCL
+
|rowspan="5"|TBD
−
| rowspan="5" |C20
+
|rowspan="5"|TBD
−
| rowspan="5" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="5" |IO
+
|rowspan="5"|TBD
−
| rowspan="5" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|I2C1_SCL
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|I3C1_SCL
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|UART1_DCB_B
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|TPM2_CH0
+
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO1_IO00
+
|TBD
 
|-
 
|-
−
| rowspan="5" |J1.103
+
|rowspan="5"|J1.58
−
| rowspan="5" |I2C1_SDA
+
|rowspan="5"|TBD
−
| rowspan="5" |CPU.I2C1_SDA
+
|rowspan="5"|TBD
−
| rowspan="5" |C21
+
|rowspan="5"|TBD
−
| rowspan="5" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="5" |IO
+
|rowspan="5"|TBD
−
| rowspan="5" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|I2C1_SDA
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|I3C1_SDA
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|UART1_RIN_B
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|TPM2_CH1
+
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO1_IO01
+
|TBD
 
|-
 
|-
−
| rowspan="6" |J1.105
+
|rowspan="5"|J1.60
−
| rowspan="6" |SAI1_TXD0
+
|rowspan="5"|TBD
−
| rowspan="6" |CPU.SAI1_TXD0//BOOT3
+
|rowspan="5"|TBD
−
| rowspan="6" |H21
+
|rowspan="5"|TBD
−
| rowspan="6" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="6" |IO
+
|rowspan="5"|TBD
−
| rowspan="6" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|SAI1_TX_DATA00
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|UART2_RTS_B
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|SPI1_SCK
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|UART1_DTR_B
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|CAN1_TX
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO1_IO13//BOOT_MODE[3]
+
|TBD
 
|-
 
|-
−
| rowspan="6" |J1.107
+
|rowspan="5"|J1.62
−
| rowspan="6" |SAI1_TXC
+
|rowspan="5"|TBD
−
| rowspan="6" |CPU.SAI1_TXC
+
|rowspan="5"|TBD
−
| rowspan="6" |G20
+
|rowspan="5"|TBD
−
| rowspan="6" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="6" |IO
+
|rowspan="5"|TBD
−
| rowspan="6" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|SAI1_TX_BCLK
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|UART2_CTS_B
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|SPI1_SIN
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|UART1_DSR_B
+
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-5
−
|CAN1_RX
+
|TBD
 
|-
 
|-
−
|Pin ALT-5
+
|rowspan="5"|J1.64
−
|GPIO1_IO12
+
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.109
+
|Pin ALT-1
−
|DGND
+
|TBD
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="1" |J1.111
+
|Pin ALT-2
−
| rowspan="1" |ADC_IN0
+
|TBD
−
| rowspan="1" |CPU.ADC_IN0
 
−
| rowspan="1" |B19
 
−
| rowspan="1" |NVCC_3V3
 
−
| rowspan="1" |IO
 
−
| rowspan="1" |
 
−
|Pin ALT-0
 
−
|ADC_IN0
 
 
|-
 
|-
−
| rowspan="1" |J1.113
+
|Pin ALT-3
−
| rowspan="1" |ADC_IN1
+
|TBD
−
| rowspan="1" |CPU.ADC_IN1
 
−
| rowspan="1" |A20
 
−
| rowspan="1" |NVCC_3V3
 
−
| rowspan="1" |IO
 
−
| rowspan="1" |
 
−
|Pin ALT-0
 
−
|ADC_IN1
 
 
|-
 
|-
−
| rowspan="1" |J1.115
+
|Pin ALT-5
−
| rowspan="1" |ADC_IN2
+
|TBD
−
| rowspan="1" |CPU.ADC_IN2
 
−
| rowspan="1" |B20
 
−
| rowspan="1" |NVCC_3V3
 
−
| rowspan="1" |IO
 
−
| rowspan="1" |
 
−
|Pin ALT-0
 
−
|ADC_IN2
 
 
|-
 
|-
−
| rowspan="1" |J1.117
+
|rowspan="5"|J1.66
−
| rowspan="1" |ADC_IN3
+
|rowspan="5"|TBD
−
| rowspan="1" |CPU.ADC_IN3
+
|rowspan="5"|TBD
−
| rowspan="1" |B21
+
|rowspan="5"|TBD
−
| rowspan="1" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="1" |IO
+
|rowspan="5"|TBD
−
| rowspan="1" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|ADC_IN3
+
|TBD
 
|-
 
|-
−
|J1.119
+
|Pin ALT-1
−
|PMIC_SCLH
+
|TBD
−
|PMIC.SCLH
 
−
|25
 
−
| -
 
−
|
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.121
+
|Pin ALT-2
−
|PMIC_SDAH
+
|TBD
−
|PMIC.SDAH
 
−
|24
 
−
| -
 
−
|
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.123
+
|Pin ALT-3
−
|PMIC_SCLL
+
|TBD
−
|PMIC.SCLL
 
−
|27
 
−
| -
 
−
|
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.125
+
|Pin ALT-5
−
|PMIC_SDAL
+
|TBD
−
|PMIC.SDAL
 
−
|26
 
−
| -
 
−
|
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="5" |J1.127
+
|rowspan="5"|J1.68
−
| rowspan="5" |I2C2_SDA
+
|rowspan="5"|TBD
−
| rowspan="5" |CPU.I2C2_SDA<br>PMIC.SDA
+
|rowspan="5"|TBD
−
| rowspan="5" |D21<br>42
+
|rowspan="5"|TBD
−
| rowspan="5" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="5" |IO
+
|rowspan="5"|TBD
−
| rowspan="5" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|I2C2_SDA
+
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|UART2_RIN_B
+
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-5
−
|TPM2_CH3
+
|TBD
 +
|-
 +
|rowspan="5"|J1.70
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|Pin ALT-5
+
|Pin ALT-3
−
|SAI1_RX_BCLK
+
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO1_IO03
+
|TBD
 
|-
 
|-
−
| rowspan="7" |J1.129
+
|rowspan="5"|J1.72
−
| rowspan="7" |I2C2_SCL
+
|rowspan="5"|TBD
−
| rowspan="7" |CPU.I2C2_SCL<br>PMIC.SCL
+
|rowspan="5"|TBD
−
| rowspan="7" |D20<br>41
+
|rowspan="5"|TBD
−
| rowspan="7" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="7" |IO
+
|rowspan="5"|TBD
−
| rowspan="7" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|I2C2_SCL
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|I3C1_PUR
+
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|UART2_DCB_B
+
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.74
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-2
−
|TPM2_CH2
+
|TBD
 
|-
 
|-
−
|Pin ALT-5
+
|Pin ALT-3
−
|SAI1_RX_SYNC
+
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO1_IO02
+
|TBD
 
|-
 
|-
−
|Pin ALT-6
+
|rowspan="5"|J1.76
−
|I3C1_PUR_B
+
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.131
+
|Pin ALT-1
−
|DGND
+
|TBD
−
|DGND
+
|-
−
| -
+
|Pin ALT-2
−
| -
+
|TBD
−
|G
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.133
+
|Pin ALT-3
−
|LVDS_CLK_N
+
|TBD
−
|CPU.LVDS_CLK_N
 
−
|A3
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.135
+
|Pin ALT-5
−
|LVDS_CLK_P
+
|TBD
−
|CPU.LVDS_CLK_P
 
−
|B3
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.137
+
|rowspan="5"|J1.78
−
|LVDS_TX0_N
+
|rowspan="5"|TBD
−
|CPU.LVDS_TX0_N
+
|rowspan="5"|TBD
−
|A5
+
|rowspan="5"|TBD
−
|VDD_ANA_1V8
+
|rowspan="5"|TBD
−
|D
+
|rowspan="5"|TBD
−
|
+
|rowspan="5"|TBD
−
|
+
|Pin ALT-0
−
|
+
|TBD
 
|-
 
|-
−
|J1.139
+
|Pin ALT-1
−
|LVDS_TX0_P
+
|TBD
−
|CPU.LVDS_TX0_P
 
−
|B5
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.141
+
|Pin ALT-2
−
|LVDS_TX1_N
+
|TBD
−
|CPU.LVDS_TX1_N
 
−
|A4
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.143
+
|Pin ALT-3
−
|LVDS_TX1_P
+
|TBD
−
|CPU.LVDS_TX1_P
 
−
|B4
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.145
+
|Pin ALT-5
−
|LVDS_TX2_N
+
|TBD
−
|CPU.LVDS_TX2_N
 
−
|A2
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.147
+
|rowspan="5"|J1.80
−
|LVDS_TX2_P
+
|rowspan="5"|TBD
−
|CPU.LVDS_TX2_P
+
|rowspan="5"|TBD
−
|B2
+
|rowspan="5"|TBD
−
|VDD_ANA_1V8
+
|rowspan="5"|TBD
−
|D
+
|rowspan="5"|TBD
−
|
+
|rowspan="5"|TBD
−
|
+
|Pin ALT-0
−
|
+
|TBD
 
|-
 
|-
−
|J1.149
+
|Pin ALT-1
−
|LVDS_TX3_N
+
|TBD
−
|CPU.LVDS_TX3_N
 
−
|B1
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.151
+
|Pin ALT-2
−
|LVDS_TX3_P
+
|TBD
−
|CPU.LVDS_TX3_P
 
−
|C1
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.153
+
|Pin ALT-3
−
|DGND
+
|TBD
−
|DGND
+
|-
−
| -
+
|Pin ALT-5
−
| -
+
|TBD
−
|G
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.155
+
|rowspan="5"|J1.82
−
|DSI_CLK_N
+
|rowspan="5"|TBD
−
|CPU.DSI_CLK_N
+
|rowspan="5"|TBD
−
|D6
+
|rowspan="5"|TBD
−
|VDD_ANA_1V8
+
|rowspan="5"|TBD
−
|D
+
|rowspan="5"|TBD
−
|
+
|rowspan="5"|TBD
−
|
+
|Pin ALT-0
−
|
+
|TBD
 
|-
 
|-
−
|J1.157
+
|Pin ALT-1
−
|DSI_CLK_P
+
|TBD
−
|CPU.DSI_CLK_P
 
−
|E6
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.159
+
|Pin ALT-2
−
|DSI_TX0_N
+
|TBD
−
|CPU.DSI_TX0_N
 
−
|A6
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.161
+
|Pin ALT-3
−
|DSI_TX0_P
+
|TBD
−
|CPU.DSI_TX0_P
 
−
|B6
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.163
+
|Pin ALT-5
−
|DSI_TX1_N
+
|TBD
−
|CPU.DSI_TX1_N
 
−
|A7
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.165
+
|rowspan="5"|J1.84
−
|DSI_TX1_P
+
|rowspan="5"|TBD
−
|CPU.DSI_TX1_P
+
|rowspan="5"|TBD
−
|B7
+
|rowspan="5"|TBD
−
|VDD_ANA_1V8
+
|rowspan="5"|TBD
−
|D
+
|rowspan="5"|TBD
−
|
+
|rowspan="5"|TBD
−
|
+
|Pin ALT-0
−
|
+
|TBD
 
|-
 
|-
−
|J1.167
+
|Pin ALT-1
−
|DSI_TX2_N
+
|TBD
−
|CPU.DSI_TX2_N
 
−
|A8
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.169
+
|Pin ALT-2
−
|DSI_TX2_P
+
|TBD
−
|CPU.DSI_TX2_P
 
−
|B8
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.171
+
|Pin ALT-3
−
|DSI_TX3_N
+
|TBD
−
|CPU.DSI_TX3_N
 
−
|A9
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.173
+
|Pin ALT-5
−
|DSI_TX3_P
+
|TBD
−
|CPU.DSI_TX3_P
 
−
|B9
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.175
 
−
|DGND
 
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="5" |J1.177
+
|rowspan="5"|J1.86
−
| rowspan="5" |SD2_CD_B
+
|rowspan="5"|TBD
−
| rowspan="5" |CPU.GPIO_IO08
+
|rowspan="5"|TBD
−
| rowspan="5" |M20
+
|rowspan="5"|TBD
−
| rowspan="5" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="5" |IO
+
|rowspan="5"|TBD
−
| rowspan="5" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC2_CD_B
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|ENET_QOS_1588_EVENT0_IN
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|I2C3_SCL
+
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-3
−
|FLEXIO1_FLEXIO00
+
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO3_IO00
+
|TBD
 
|-
 
|-
−
| rowspan="8" |J1.179
+
|rowspan="5"|J1.88
−
| rowspan="8" |GPIO_IO00
+
|rowspan="5"|TBD
−
| rowspan="8" |CPU.GPIO_IO00
+
|rowspan="5"|TBD
−
| rowspan="8" |J21
+
|rowspan="5"|TBD
−
| rowspan="8" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="8" |IO
+
|rowspan="5"|TBD
−
| rowspan="8" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|GPIO2_IO00
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|I2C3_SDA
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAM_CLK
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_CLK
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|SPI6_PCS0
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|UART5_TX
+
|TBD
−
|-
 
−
|Pin ALT-6
 
−
|I2C5_SDA
 
−
|-
 
−
|Pin ALT-7
 
−
|FLEXIO1_FLEXIO00
 
 
|-
 
|-
−
| rowspan="8" |J1.181
+
|rowspan="5"|J1.90
−
| rowspan="8" |GPIO_IO03
+
|rowspan="5"|TBD
−
| rowspan="8" |CPU.GPIO_IO03
+
|rowspan="5"|TBD
−
| rowspan="8" |K21
+
|rowspan="5"|TBD
−
| rowspan="8" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="8" |IO
+
|rowspan="5"|TBD
−
| rowspan="8" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|GPIO2_IO03
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|I2C4_SCL
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAM_HSYNC
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_HSYNC
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|SPI6_SCK
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|UART5_RTS_B
+
|TBD
 
|-
 
|-
−
|Pin ALT-6
+
|rowspan="5"|J1.92
−
|I2C6_SCL
+
|rowspan="5"|TBD
−
|-
+
|rowspan="5"|TBD
−
|Pin ALT-7
+
|rowspan="5"|TBD
−
|FLEXIO1_FLEXIO03
+
|rowspan="5"|TBD
−
|-
+
|rowspan="5"|TBD
−
| rowspan="8" |J1.183
+
|rowspan="5"|TBD
−
| rowspan="8" |GPIO_IO01
 
−
| rowspan="8" |CPU.GPIO_IO01
 
−
| rowspan="8" |K21
 
−
| rowspan="8" |NVCC_3V3
 
−
| rowspan="8" |IO
 
−
| rowspan="8" |
 
 
|Pin ALT-0
 
|Pin ALT-0
−
|GPIO2_IO01
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|I2C3_SCL
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAM_DATA00
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DE
+
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|rowspan="5"|J1.94
−
|SPI6_SIN
+
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin ALT-5
+
|Pin ALT-1
−
|UART5_RX
+
|TBD
 
|-
 
|-
−
|Pin ALT-6
+
|Pin ALT-2
−
|I2C5_SCL
+
|TBD
 
|-
 
|-
−
|Pin ALT-7
+
|Pin ALT-3
−
|FLEXIO1_FLEXIO01
+
|TBD
 
|-
 
|-
−
|J1.185
+
|Pin ALT-5
−
| -
+
|TBD
−
| -
 
−
| -
 
−
| -
 
−
|
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="5" |J1.187
+
|rowspan="5"|J1.96
−
| rowspan="5" |UART1_TXD
+
|rowspan="5"|TBD
−
| rowspan="5" |CPU.UART1_TXD//BOOT0
+
|rowspan="5"|TBD
−
| rowspan="5" |E21
+
|rowspan="5"|TBD
−
| rowspan="5" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="5" |IO
+
|rowspan="5"|TBD
−
| rowspan="5" |Used as default Linux console (Cortex-A55)
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|UART1_TX
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|SECO_UART_TX
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|SPI2_PCS0
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|TPM1_CH1
+
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO1_IO05//BOOT_MODE[0]
+
|TBD
 
|-
 
|-
−
| rowspan="5" |J1.189
+
|rowspan="5"|J1.98
−
| rowspan="5" |UART1_RXD
+
|rowspan="5"|TBD
−
| rowspan="5" |CPU.UART1_RXD
+
|rowspan="5"|TBD
−
| rowspan="5" |E20
+
|rowspan="5"|TBD
−
| rowspan="5" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="5" |IO
+
|rowspan="5"|TBD
−
| rowspan="5" |Used as default Linux console (Cortex-A55)
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|UART1_RX
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|SECO_UART_RX
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|SPI2_SIN
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|TPM1_CH0
+
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO1_IO04
+
|TBD
 
|-
 
|-
−
| rowspan="8" |J1.191
+
|rowspan="5"|J1.100
−
| rowspan="8" |GPIO_IO12
+
|rowspan="5"|TBD
−
| rowspan="8" |CPU.GPIO_IO12
+
|rowspan="5"|TBD
−
| rowspan="8" |N20
+
|rowspan="5"|TBD
−
| rowspan="8" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="8" |IO
+
|rowspan="5"|TBD
−
| rowspan="8" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|GPIO2_IO12
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|TPM3_CH2
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|PDM_BIT_STREAM02
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA08
+
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-5
−
|SPI8_PCS0
+
|TBD
 +
|-
 +
|rowspan="5"|J1.102
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin ALT-5
+
|Pin ALT-1
−
|UART8_TX
+
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|Pin ALT-6
+
|Pin ALT-3
−
|I2C8_SDA
+
|TBD
 
|-
 
|-
−
|Pin ALT-7
+
|Pin ALT-5
−
|SAI3_RX_SYNC
+
|TBD
 
|-
 
|-
−
| rowspan="8" |J1.193
+
|rowspan="5"|J1.104
−
| rowspan="8" |GPIO_IO13
+
|rowspan="5"|TBD
−
| rowspan="8" |CPU.GPIO_IO13
+
|rowspan="5"|TBD
−
| rowspan="8" |N21
+
|rowspan="5"|TBD
−
| rowspan="8" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="8" |IO
+
|rowspan="5"|TBD
−
| rowspan="8" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|GPIO2_IO13
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|TPM4_CH2
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|PDM_BIT_STREAM03
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA09
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|SPI8_SIN
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|UART8_RX
+
|TBD
−
|-
 
−
|Pin ALT-6
 
−
|I2C8_SCL
 
 
|-
 
|-
−
|Pin ALT-7
+
|rowspan="5"|J1.106
−
|FLEXIO1_FLEXIO13
+
|rowspan="5"|TBD
−
|-
+
|rowspan="5"|TBD
−
| rowspan="8" |J1.195
+
|rowspan="5"|TBD
−
| rowspan="8" |GPIO_IO02
+
|rowspan="5"|TBD
−
| rowspan="8" |CPU.GPIO_IO02
+
|rowspan="5"|TBD
−
| rowspan="8" |K21
+
|rowspan="5"|TBD
−
| rowspan="8" |NVCC_3V3
 
−
| rowspan="8" |IO
 
−
| rowspan="8" |
 
 
|Pin ALT-0
 
|Pin ALT-0
−
|GPIO2_IO13
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|I2C4_SDA
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAM_VSYNC
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_VSYNC
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|SPI6_SOUT
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|UART5_CTS_B
+
|TBD
 
|-
 
|-
−
|Pin ALT-6
+
|rowspan="5"|J1.108
−
|I2C6_SDA
+
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin ALT-7
+
|Pin ALT-1
−
|FLEXIO1_FLEXIO02
+
|TBD
 
|-
 
|-
−
|J1.197
+
|Pin ALT-2
−
| -
+
|TBD
−
| -
+
|-
−
| -
+
|Pin ALT-3
−
| -
+
|TBD
−
|
+
|-
−
|
+
|Pin ALT-5
−
|
+
|TBD
−
|
 
 
|-
 
|-
−
| rowspan="7" |J1.199
+
|rowspan="5"|J1.110
−
| rowspan="7" |PDM_BIT_STREAM0
+
|rowspan="5"|TBD
−
| rowspan="7" |CPU.PDM_BIT_STREAM0
+
|rowspan="5"|TBD
−
| rowspan="7" |J17
+
|rowspan="5"|TBD
−
| rowspan="7" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="7" |IO
+
|rowspan="5"|TBD
−
| rowspan="7" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|PDM_BIT_STREAM00
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|MQS1_RIGHT
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|SPI1_PCS1
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|TPM1_EXTCLK
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|LPTMR1_ALT2
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO1_IO09
+
|TBD
−
|-
 
−
|Pin ALT-6
 
−
|CAN1_RX
 
 
|-
 
|-
−
| rowspan="5" |J1.201
+
|rowspan="5"|J1.112
−
| rowspan="5" |PDM_CLK
+
|rowspan="5"|TBD
−
| rowspan="5" |CPU.PDM_CLK
+
|rowspan="5"|TBD
−
| rowspan="5" |G17
+
|rowspan="5"|TBD
−
| rowspan="5" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="5" |IO
+
|rowspan="5"|TBD
−
| rowspan="5" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|PDM_CLK
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|MQS1_LEFT
+
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-3
−
|LPTMR1_ALT1
+
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO1_IO08
+
|TBD
 +
|-
 +
|rowspan="5"|J1.114
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|Pin ALT-6
+
|Pin ALT-2
−
|CAN1_TX
+
|TBD
 
|-
 
|-
−
|J1.203
+
|Pin ALT-3
−
|DGND
+
|TBD
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
−
|}
 
−
 
 
−
==Pinout Table EVEN  pins declaration ==
 
−
{| class="wikitable"
 
−
! latexfontsize="scriptsize" | Pin
 
−
! latexfontsize="scriptsize" | Pin Name
 
−
! latexfontsize="scriptsize" | Internal Connections
 
−
! latexfontsize="scriptsize" | Ball/pin #
 
−
! latexfontsize="scriptsize" |Voltage
 
−
domain
 
−
! latexfontsize="scriptsize" | Type
 
−
! latexfontsize="scriptsize" | Notes
 
−
! colspan="2" latexfontsize="scriptsize" | Alternative Functions
 
 
|-
 
|-
−
|J1.2
+
|Pin ALT-5
−
|DGND
+
|TBD
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.4
+
|rowspan="5"|J1.116
−
|3.3VIN
+
|rowspan="5"|TBD
−
|INPUT VOLTAGE
+
|rowspan="5"|TBD
−
| -
+
|rowspan="5"|TBD
−
|3.3VIN
+
|rowspan="5"|TBD
−
|S
+
|rowspan="5"|TBD
−
|
+
|rowspan="5"|TBD
−
|
+
|Pin ALT-0
−
|
+
|TBD
 
|-
 
|-
−
|J1.6
+
|Pin ALT-1
−
|3.3VIN
+
|TBD
−
|INPUT VOLTAGE
 
−
| -
 
−
|3.3VIN
 
−
|S
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.8
+
|Pin ALT-2
−
|3.3VIN
+
|TBD
−
|INPUT VOLTAGE
 
−
| -
 
−
|3.3VIN
 
−
|S
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.10
+
|Pin ALT-3
−
|3.3VIN
+
|TBD
−
|INPUT VOLTAGE
+
|-
−
| -
+
|Pin ALT-5
−
|3.3VIN
+
|TBD
−
|S
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.12
+
|rowspan="5"|J1.118
−
|DGND
+
|rowspan="5"|TBD
−
|DGND
+
|rowspan="5"|TBD
−
| -
+
|rowspan="5"|TBD
−
| -
+
|rowspan="5"|TBD
−
|G
+
|rowspan="5"|TBD
−
|
+
|rowspan="5"|TBD
−
|
+
|Pin ALT-0
−
|
+
|TBD
 
|-
 
|-
−
|J1.14
+
|Pin ALT-1
−
|SYS_NRST
+
|TBD
−
|PMIC.PMIC_RST_B
 
−
|8
 
−
|
 
−
|I
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.16
+
|Pin ALT-2
−
|CPU_ON_OFF
+
|TBD
−
|CPU.ON_OFF
 
−
|A19
 
−
|NVCC_3V3
 
−
|I
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.18
+
|Pin ALT-3
−
|SOM_PGOOD
+
|TBD
−
| -
 
−
| -
 
−
|NVCC_3V3
 
−
|O
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.20
+
|Pin ALT-5
−
|BOOT_MODE_SEL
+
|TBD
−
|BOOT MODE SELECTION
 
−
| -
 
−
|NVCC_3V3
 
−
|I
 
−
|internal pull-up to NVCC_3V3
 
−
|
 
−
|
 
−
|-
 
−
|J1.22
 
−
|CPU_PORn
 
−
|CPU.POR_B
 
−
PMIC.POR_B
 
−
|A16
 
−
9
 
−
|NVCC_BBSM_1V8
 
−
|I/O
 
−
|internal pull-up 100k to NVCC_BBSM_1V8
 
−
|
 
−
|
 
−
|-
 
−
|J1.24
 
−
|PMIC_ON_REQ
 
−
|PMIC.PMIC_ON_REQ
 
−
|39
 
−
|NVCC_BBSM_1V8
 
−
|I
 
−
|internal pull-up 100k to NVCC_BBSM_1V8
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="6" |J1.26
+
|rowspan="5"|J1.120
−
| rowspan="6" |PDM_BIT_STREAM1
+
|rowspan="5"|TBD
−
| rowspan="6" |CPU.PDM_BIT_STREAM1
+
|rowspan="5"|TBD
−
| rowspan="6" |JG18
+
|rowspan="5"|TBD
−
| rowspan="6" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="6" |IO
+
|rowspan="5"|TBD
−
| rowspan="6" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|PDM_BIT_STREAM01
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|NMI_GLUE_NMI
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|SPI2_PCS1
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|TPM2_EXTCLK
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|LPTMR1_ALT3
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO1_IO10
+
|TBD
 
|-
 
|-
−
| rowspan="2" |J1.28
+
|rowspan="5"|J1.122
−
| rowspan="2" |WDOG_ANY
+
|rowspan="5"|TBD
−
| rowspan="2" |CPU.PDM_BIT_STREAM1
+
|rowspan="5"|TBD
−
| rowspan="2" |JG18
+
|rowspan="5"|TBD
−
| rowspan="2" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="2" |IO
+
|rowspan="5"|TBD
−
| rowspan="2" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|WDOG1_WDOG_ANY
+
|TBD
 
|-
 
|-
−
|Pin ALT-5
+
|Pin ALT-1
−
|GPIO1_IO15
+
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J1.30
+
|Pin ALT-3
−
|DGND
+
|TBD
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.32
+
|Pin ALT-5
−
|PMIC_STBY_REQ
+
|TBD
−
|PMIC.PMIC_STBY_REQ
 
−
|40
 
−
|NVCC_BBSM_1V8
 
−
|O
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="8" |J1.34
+
|rowspan="5"|J1.124
−
| rowspan="8" |GPIO_IO17
+
|rowspan="5"|TBD
−
| rowspan="8" |CPU.GPIO_IO17
+
|rowspan="5"|TBD
−
| rowspan="8" |R20
+
|rowspan="5"|TBD
−
| rowspan="8" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="8" |IO
+
|rowspan="5"|TBD
−
| rowspan="8" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|GPIO2_IO17
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|SAI3_MCLK
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAM_DATA08
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA13
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|UART3_RTS_B
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|SPI4_PCS1
+
|TBD
−
|-
 
−
|Pin ALT-6
 
−
|UART4_RTS_B
 
−
|-
 
−
|Pin ALT-7
 
−
|FLEXIO1_FLEXIO17
 
 
|-
 
|-
−
| rowspan="8" |J1.36
+
|rowspan="5"|J1.126
−
| rowspan="8" |GPIO_IO21
+
|rowspan="5"|TBD
−
| rowspan="8" |CPU.GPIO_IO21
+
|rowspan="5"|TBD
−
| rowspan="8" |T21
+
|rowspan="5"|TBD
−
| rowspan="8" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="8" |IO
+
|rowspan="5"|TBD
−
| rowspan="8" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|GPIO2_IO21
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|SAI3_TX_DATA00
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|PDM_CLK
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA17
+
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-5
−
|SPI5_SCK
+
|TBD
 +
|-
 +
|rowspan="5"|J1.128
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|Pin ALT-5
+
|Pin ALT-2
−
|SPI4_SCK
+
|TBD
 
|-
 
|-
−
|Pin ALT-6
+
|Pin ALT-3
−
|TPM4_CH1
+
|TBD
 
|-
 
|-
−
|Pin ALT-7
+
|Pin ALT-5
−
|SAI3_RX_BCLK
+
|TBD
 
|-
 
|-
−
| rowspan="3" |J1.38
+
|rowspan="5"|J1.130
−
| rowspan="3" |GPIO_IO29
+
|rowspan="5"|TBD
−
| rowspan="3" |CPU.GPIO_IO29
+
|rowspan="5"|TBD
−
| rowspan="3" |Y21
+
|rowspan="5"|TBD
−
| rowspan="3" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="3" |IO
+
|rowspan="5"|TBD
−
| rowspan="3" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|GPIO2_IO29
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|I2C3_SCL
+
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|Pin ALT-7
+
|Pin ALT-5
−
|FLEXIO1_FLEXIO29
+
|TBD
 
|-
 
|-
−
| rowspan="8" |J1.40
+
|rowspan="5"|J1.132
−
| rowspan="8" |GPIO_IO07
+
|rowspan="5"|TBD
−
| rowspan="8" |CPU.GPIO_IO07
+
|rowspan="5"|TBD
−
| rowspan="8" |L21
+
|rowspan="5"|TBD
−
| rowspan="8" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="8" |IO
+
|rowspan="5"|TBD
−
| rowspan="8" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|GPIO2_IO07
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|SPI3_PCS1
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAM_DATA01
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA03
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|SPI7_SCK
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|UART6_RTS_B
+
|TBD
−
|-
 
−
|Pin ALT-6
 
−
|I2C7_SCL
 
−
|-
 
−
|Pin ALT-7
 
−
|FLEXIO1_FLEXIO07
 
 
|-
 
|-
−
| rowspan="8" |J1.42
+
|rowspan="5"|J1.134
−
| rowspan="8" |GPIO_IO25//CAN_H
+
|rowspan="5"|TBD
−
| rowspan="8" |CPU.GPIO_IO25
+
|rowspan="5"|TBD
−
CAN.CANH
+
|rowspan="5"|TBD
−
| rowspan="8" |V21
+
|rowspan="5"|TBD
−
7
+
|rowspan="5"|TBD
−
| rowspan="8" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="8" |IO
 
−
| rowspan="8" |optional CAN transceiver
 
 
|Pin ALT-0
 
|Pin ALT-0
−
|GPIO2_IO25
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|USDHC3_DATA1
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAN2_TX
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA21
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|TPM4_CH3
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|JTAG_MUX_TCK
+
|TBD
 
|-
 
|-
−
|Pin ALT-6
+
|rowspan="5"|J1.136
−
|SPI7_PCS1
+
|rowspan="5"|TBD
−
|-
+
|rowspan="5"|TBD
−
|Pin ALT-7
+
|rowspan="5"|TBD
−
|FLEXIO1_FLEXIO25
+
|rowspan="5"|TBD
−
|-
+
|rowspan="5"|TBD
−
| rowspan="8" |J1.44
+
|rowspan="5"|TBD
−
| rowspan="8" |GPIO_IO27//CAN_L
 
−
| rowspan="8" |CPU.GPIO_IO27
 
−
CAN.CANL
 
−
| rowspan="8" |W21
 
−
6
 
−
| rowspan="8" |NVCC_3V3
 
−
| rowspan="8" |IO
 
−
| rowspan="8" |optional CAN transceiver
 
 
|Pin ALT-0
 
|Pin ALT-0
−
|GPIO2_IO27
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|USDHC3_DATA3
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|CAN2_RX
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA23
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|TPM6_CH3
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|JTAG_MUX_TMS
+
|TBD
−
|-
 
−
|Pin ALT-6
 
−
|SPI5_PCS1
 
−
|-
 
−
|Pin ALT-7
 
−
|FLEXIO1_FLEXIO27
 
 
|-
 
|-
−
| rowspan="7" |J1.46
+
|rowspan="5"|J1.138
−
| rowspan="7" |GPIO_IO24
+
|rowspan="5"|TBD
−
| rowspan="7" |CPU.GPIO_IO24
+
|rowspan="5"|TBD
−
| rowspan="7" |U21
+
|rowspan="5"|TBD
−
| rowspan="7" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="7" |IO
+
|rowspan="5"|TBD
−
| rowspan="7" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|GPIO2_IO24
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|USDHC3_DATA0
+
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA20
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|TPM3_CH3
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|JTAG_MUX_TDO
+
|TBD
−
|-
 
−
|Pin ALT-6
 
−
|SPI6_PSC1
 
 
|-
 
|-
−
|Pin ALT-7
+
|rowspan="5"|J1.140
−
|FLEXIO1_FLEXIO24
+
|rowspan="5"|TBD
−
|-
+
|rowspan="5"|TBD
−
| rowspan="3" |J1.48
+
|rowspan="5"|TBD
−
| rowspan="3" |GPIO_IO28
+
|rowspan="5"|TBD
−
| rowspan="3" |CPU.GPIO_IO28
+
|rowspan="5"|TBD
−
| rowspan="3" |W20
+
|rowspan="5"|TBD
−
| rowspan="3" |NVCC_3V3
 
−
| rowspan="3" |IO
 
−
| rowspan="3" |
 
 
|Pin ALT-0
 
|Pin ALT-0
−
|GPIO2_IO28
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|I2C3_SDA
+
|TBD
 
|-
 
|-
−
|Pin ALT-7
+
|Pin ALT-2
−
|FLEXIO1_FLEXIO28
+
|TBD
 
|-
 
|-
−
| rowspan="3" |J1.50
+
|Pin ALT-3
−
| rowspan="3" |CCM_CLK01
+
|TBD
−
| rowspan="3" |CPU.CCM_CLK01
 
−
| rowspan="3" |AA2
 
−
| rowspan="3" |NVCC_3V3
 
−
| rowspan="3" |IO
 
−
| rowspan="3" |
 
−
|Pin ALT-0
 
−
|CCMSRCGPCMIX_CLK01
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO1_FLEXIO26
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO3_IO26
+
|TBD
 
|-
 
|-
−
| rowspan="3" |J1.52
+
|rowspan="5"|J1.142
−
| rowspan="3" |CCM_CLK02
+
|rowspan="5"|TBD
−
| rowspan="3" |CPU.CCM_CLK02
+
|rowspan="5"|TBD
−
| rowspan="3" |Y3
+
|rowspan="5"|TBD
−
| rowspan="3" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="3" |IO
+
|rowspan="5"|TBD
−
| rowspan="3" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|CCMSRCGPCMIX_CLK02
+
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-1
−
|FLEXIO1_FLEXIO27
+
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO3_IO27
+
|TBD
 
|-
 
|-
−
| rowspan="3" |J1.54
+
|rowspan="5"|J1.144
−
| rowspan="3" |CCM_CLK03
+
|rowspan="5"|TBD
−
| rowspan="3" |CPU.CCM_CLK03
+
|rowspan="5"|TBD
−
| rowspan="3" |U4
+
|rowspan="5"|TBD
−
| rowspan="3" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="3" |IO
+
|rowspan="5"|TBD
−
| rowspan="3" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|CCMSRCGPCMIX_CLK01
+
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-1
−
|FLEXIO2_FLEXIO28
+
|TBD
 
|-
 
|-
−
|Pin ALT-5
+
|Pin ALT-2
−
|GPIO4_IO28
+
|TBD
 
|-
 
|-
−
|J1.56
+
|Pin ALT-3
−
|DGND
+
|TBD
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.58
+
|Pin ALT-5
−
|ETH_RSTn
+
|TBD
−
|LAN.RESETn
 
−
|43
 
−
|NVCC_3V3
 
−
|I
 
−
|Hardware mounting option
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.60
+
|rowspan="5"|J1.146
−
|ETH_INTn
+
|rowspan="5"|TBD
−
|LAN.INT_N
+
|rowspan="5"|TBD
−
|39
+
|rowspan="5"|TBD
−
|NVCC_3V3
+
|rowspan="5"|TBD
−
|O
+
|rowspan="5"|TBD
−
|Hardware mounting option
+
|rowspan="5"|TBD
−
|
 
−
|
 
−
|-
 
−
| rowspan="6" |J1.62
 
−
| rowspan="6" |SAI1_RXD0
 
−
| rowspan="6" |CPU.SAI1_RXD0
 
−
| rowspan="6" |H20
 
−
| rowspan="6" |NVCC_3V3
 
−
| rowspan="6" |IO
 
−
| rowspan="6" |
 
 
|Pin ALT-0
 
|Pin ALT-0
−
|SAI1_RX_DATA00
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|SAI1_MCLK
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|SPI1_SOUT
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|UART2_DSR_B
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|MQS1_RIGHT
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO1_IO14
+
|TBD
 
|-
 
|-
−
| rowspan="3" |J1.64
+
|rowspan="5"|J1.148
−
| rowspan="3" |CCM_CLK04
+
|rowspan="5"|TBD
−
| rowspan="3" |CPU.CCM_CLK04
+
|rowspan="5"|TBD
−
| rowspan="3" |V4
+
|rowspan="5"|TBD
−
| rowspan="3" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="3" |IO
+
|rowspan="5"|TBD
−
| rowspan="3" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|CCMSRCGPCMIX_CLK04
+
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-1
−
|FLEXIO2_FLEXIO29
+
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO4_IO29
+
|TBD
 
|-
 
|-
−
| rowspan="8" |J1.66
+
|rowspan="5"|J1.150
−
| rowspan="8" |GPIO_IO16
+
|rowspan="5"|TBD
−
| rowspan="8" |CPU.GPIO_IO16
+
|rowspan="5"|TBD
−
| rowspan="8" |R21
+
|rowspan="5"|TBD
−
| rowspan="8" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="8" |IO
+
|rowspan="5"|TBD
−
| rowspan="8" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|GPIO2_IO16
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|SAI3_TX_BCLK
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|PDM_BIT_STREAM02
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA12
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|UART3_CTS_B
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|SPI4_PCS2
+
|TBD
−
|-
 
−
|Pin ALT-6
 
−
|UART4_CTS_B
 
−
|-
 
−
|Pin ALT-7
 
−
|FLEXIO1_FLEXIO16
 
 
|-
 
|-
−
| rowspan="8" |J1.68
+
|rowspan="5"|J1.152
−
| rowspan="8" |GPIO_IO19
+
|rowspan="5"|TBD
−
| rowspan="8" |CPU.GPIO_IO19
+
|rowspan="5"|TBD
−
| rowspan="8" |R17
+
|rowspan="5"|TBD
−
| rowspan="8" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="8" |IO
+
|rowspan="5"|TBD
−
| rowspan="8" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|GPIO2_IO19
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|SAI3_RX_SYNC
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|PDM_BIT_STREAM03
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA15
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|SPI5_SIN
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|SPI4_SIN
+
|TBD
−
|-
 
−
|Pin ALT-6
 
−
|TPM4_CH2
 
−
|-
 
−
|Pin ALT-7
 
−
|SAI3_TX_DATA00
 
 
|-
 
|-
−
| rowspan="8" |J1.70
+
|rowspan="5"|J1.154
−
| rowspan="8" |GPIO_IO26
+
|rowspan="5"|TBD
−
| rowspan="8" |CPU.GPIO_IO26
+
|rowspan="5"|TBD
−
| rowspan="8" |V20
+
|rowspan="5"|TBD
−
| rowspan="8" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="8" |IO
+
|rowspan="5"|TBD
−
| rowspan="8" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|GPIO2_IO26
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|USDHC3_DATA2
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|PDM_BIT_STREAM01
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA22
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|TPM3_CH3
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|JTAG_MUX_TDI
+
|TBD
 
|-
 
|-
−
|Pin ALT-6
+
|rowspan="5"|J1.156
−
|SPI8_PCS1
+
|rowspan="5"|TBD
−
|-
+
|rowspan="5"|TBD
−
|Pin ALT-7
+
|rowspan="5"|TBD
−
|SAI3_TX_SYNC
+
|rowspan="5"|TBD
−
|-
+
|rowspan="5"|TBD
−
| rowspan="8" |J1.72
+
|rowspan="5"|TBD
−
| rowspan="8" |GPIO_IO20
+
|Pin ALT-0
−
| rowspan="8" |CPU.GPIO_IO20
+
|TBD
−
| rowspan="8" |T20
 
−
| rowspan="8" |NVCC_3V3
 
−
| rowspan="8" |IO
 
−
| rowspan="8" |
 
−
|Pin ALT-0
 
−
|GPIO2_IO20
 
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|SAI3_RX_DATA00
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|PDM_BIT_STREAM00
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA16
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|SPI5_SOUT
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|SPI4_SOUT
+
|TBD
−
|-
 
−
|Pin ALT-6
 
−
|TPM3_CH1
 
 
|-
 
|-
−
|Pin ALT-7
+
|rowspan="5"|J1.158
−
|FLEXIO1_FLEXIO20
+
|rowspan="5"|TBD
−
|-
+
|rowspan="5"|TBD
−
| rowspan="8" |J1.74
+
|rowspan="5"|TBD
−
| rowspan="8" |GPIO_IO22
+
|rowspan="5"|TBD
−
| rowspan="8" |CPU.GPIO_IO22
+
|rowspan="5"|TBD
−
| rowspan="8" |U18
+
|rowspan="5"|TBD
−
| rowspan="8" |NVCC_3V3
 
−
| rowspan="8" |IO
 
−
| rowspan="8" |
 
 
|Pin ALT-0
 
|Pin ALT-0
−
|GPIO2_IO22
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|USDHC3_CLK
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|SPDIF_IN
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA18
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|TPM5_CH1
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|TPM6_EXTCLK
+
|TBD
−
|-
 
−
|Pin ALT-6
 
−
|I2C5_SDA
 
 
|-
 
|-
−
|Pin ALT-7
+
|rowspan="5"|J1.160
−
|FLEXIO1_FLEXIO22
+
|rowspan="5"|TBD
−
|-
+
|rowspan="5"|TBD
−
| rowspan="7" |J1.76
+
|rowspan="5"|TBD
−
| rowspan="7" |GPIO_IO23
+
|rowspan="5"|TBD
−
| rowspan="7" |CPU.GPIO_IO23
+
|rowspan="5"|TBD
−
| rowspan="7" |U20
+
|rowspan="5"|TBD
−
| rowspan="7" |NVCC_3V3
 
−
| rowspan="7" |IO
 
−
| rowspan="7" |
 
 
|Pin ALT-0
 
|Pin ALT-0
−
|GPIO2_IO23
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|USDHC3_CMD
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|SPDIF_OUT
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA19
+
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-5
−
|TPM6_CH1
+
|TBD
−
|-
 
−
|Pin ALT-6
 
−
|I2C5_SCL
 
 
|-
 
|-
−
|Pin ALT-7
+
|rowspan="5"|J1.162
−
|FLEXIO1_FLEXIO23
+
|rowspan="5"|TBD
−
|-
+
|rowspan="5"|TBD
−
| rowspan="8" |J1.78
+
|rowspan="5"|TBD
−
| rowspan="8" |GPIO_IO05
+
|rowspan="5"|TBD
−
| rowspan="8" |CPU.GPIO_IO05
+
|rowspan="5"|TBD
−
| rowspan="8" |L18
+
|rowspan="5"|TBD
−
| rowspan="8" |NVCC_3V3
 
−
| rowspan="8" |IO
 
−
| rowspan="8" |
 
 
|Pin ALT-0
 
|Pin ALT-0
−
|GPIO2_IO05
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|TPM4_CH0
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|PDM_BIT_STREAM00
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA01
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|SPI7_SIN
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|UART6_RX
+
|TBD
−
|-
 
−
|Pin ALT-6
 
−
|I2C6_SCL
 
 
|-
 
|-
−
|Pin ALT-7
+
|rowspan="5"|J1.164
−
|FLEXIO1_FLEXIO05
+
|rowspan="5"|TBD
−
|-
+
|rowspan="5"|TBD
−
| rowspan="8" |J1.80
+
|rowspan="5"|TBD
−
| rowspan="8" |GPIO_IO04
+
|rowspan="5"|TBD
−
| rowspan="8" |CPU.GPIO_IO04
+
|rowspan="5"|TBD
−
| rowspan="8" |L17
+
|rowspan="5"|TBD
−
| rowspan="8" |NVCC_3V3
 
−
| rowspan="8" |IO
 
−
| rowspan="8" |
 
 
|Pin ALT-0
 
|Pin ALT-0
−
|GPIO2_IO04
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|TPM3_CH0
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|PDM_CLK
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|DISP_DATA00
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|SPI7_PCS0
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|UART6_TX
+
|TBD
 
|-
 
|-
−
|Pin ALT-6
+
|rowspan="5"|J1.166
−
|I2C6_SDA
+
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin ALT-7
+
|Pin ALT-1
−
|FLEXIO1_FLEXIO04
+
|TBD
 
|-
 
|-
−
|J1.82
+
|Pin ALT-2
−
|DGND
+
|TBD
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="1" |J1.84
+
|Pin ALT-3
−
| rowspan="1" |TAMPER0
+
|TBD
−
| rowspan="1" |CPU.TAMPER0
 
−
| rowspan="1" |B16
 
−
| rowspan="1" |NVCC_3V3
 
−
| rowspan="1" |I
 
−
| rowspan="1" |
 
−
|Pin ALT-0
 
−
|BBSMMIX.TAMPER0
 
 
|-
 
|-
−
| rowspan="1" |J1.86
+
|Pin ALT-5
−
| rowspan="1" |TAMPER1
+
|TBD
−
| rowspan="1" |CPU.TAMPER1
 
−
| rowspan="1" |F14
 
−
| rowspan="1" |NVCC_3V3
 
−
| rowspan="1" |I
 
−
| rowspan="1" |
 
−
|Pin ALT-0
 
−
|BBSMMIX.TAMPER1
 
 
|-
 
|-
−
| rowspan="2" |J1.88
+
|rowspan="5"|J1.168
−
| rowspan="2" |CLKIN1
+
|rowspan="5"|TBD
−
| rowspan="2" |CPU.CLKIN1
+
|rowspan="5"|TBD
−
| rowspan="2" |B17
+
|rowspan="5"|TBD
−
| rowspan="2" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="2" |I
+
|rowspan="5"|TBD
−
| rowspan="2" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|ANAMIX.CLKIN1
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|ANAMIX.ESD_DIODE
+
|TBD
 
|-
 
|-
−
| rowspan="2" |J1.90
+
|Pin ALT-2
−
| rowspan="2" |CLKIN2
+
|TBD
−
| rowspan="2" |CPU.CLKIN2
+
|-
−
| rowspan="2" |A18
+
|Pin ALT-3
−
| rowspan="2" |NVCC_3V3
+
|TBD
−
| rowspan="2" |I
 
−
| rowspan="2" |
 
−
|Pin ALT-0
 
−
|ANAMIX.CLKIN2
 
 
|-
 
|-
−
|Pin ALT-1
+
|Pin ALT-5
−
|ANAMIX.ATX
+
|TBD
 
|-
 
|-
−
| rowspan="6" |J1.92
+
|rowspan="5"|J1.170
−
| rowspan="6" |JTAG_TDI
+
|rowspan="5"|TBD
−
| rowspan="6" |CPU.DAP_TDI
+
|rowspan="5"|TBD
−
| rowspan="6" |W1
+
|rowspan="5"|TBD
−
| rowspan="6" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="6" |IO
+
|rowspan="5"|TBD
−
| rowspan="6" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|JTAG_MUX_TDI
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|MQS2_LEFT
+
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|CAN2_TX
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO30
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO3_IO28
+
|TBD
−
|-
 
−
|Pin ALT-6
 
−
|UART5_RX
 
 
|-
 
|-
−
| rowspan="4" |J1.94
+
|rowspan="5"|J1.172
−
| rowspan="4" |JTAG_TMS
+
|rowspan="5"|TBD
−
| rowspan="4" |CPU.DAP_TMS_SWDIO
+
|rowspan="5"|TBD
−
| rowspan="4" |W2
+
|rowspan="5"|TBD
−
| rowspan="4" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="4" |IO
+
|rowspan="5"|TBD
−
| rowspan="4" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|JTAG_MUX_TMS
+
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-1
−
|FLEXIO2_FLEXIO31
+
|TBD
 
|-
 
|-
−
|Pin ALT-5
+
|Pin ALT-2
−
|GPIO3_IO29
+
|TBD
 
|-
 
|-
−
|Pin ALT-6
+
|Pin ALT-3
−
|UART5_RTS_B
+
|TBD
−
|-
 
−
| rowspan="4" |J1.96
 
−
| rowspan="4" |JTAG_TMS
 
−
| rowspan="4" |CPU.DAP_TCLK_SWCLK
 
−
| rowspan="4" |Y1
 
−
| rowspan="4" |NVCC_3V3
 
−
| rowspan="4" |IO
 
−
| rowspan="4" |
 
−
|Pin ALT-0
 
−
|JTAG_MUX_TCK
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO1_FLEXIO30
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO3_IO30
+
|TBD
−
|-
 
−
|Pin ALT-6
 
−
|UART5_CTS_B
 
 
|-
 
|-
−
| rowspan="6" |J1.98
+
|rowspan="5"|J1.174
−
| rowspan="6" |JTAG_TDO
+
|rowspan="5"|TBD
−
| rowspan="6" |CPU.DAP_TDO_TRACE_SWO
+
|rowspan="5"|TBD
−
| rowspan="6" |W1
+
|rowspan="5"|TBD
−
| rowspan="6" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="6" |IO
+
|rowspan="5"|TBD
−
| rowspan="6" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|JTAG_MUX_TDO
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|MQS2_RIGHT
+
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|CAN2_RX
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO1_FLEXIO31
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO3_IO31
+
|TBD
 
|-
 
|-
−
|Pin ALT-6
+
|rowspan="5"|J1.176
−
|UART5_TX
+
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J1.100
+
|Pin ALT-2
−
|DGND
+
|TBD
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.102
+
|Pin ALT-3
−
|CSI_CLK_N
+
|TBD
−
|CPU.MIPI_CSI1_CLK_N
 
−
|D10
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.104
+
|Pin ALT-5
−
|CSI_CLK_P
+
|TBD
−
|CPU.MIPI_CSI1_CLK_P
 
−
|E10
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.106
+
|rowspan="5"|J1.178
−
|CSI_D0_N
+
|rowspan="5"|TBD
−
|CPU.MIPI_CSI1_D0_N
+
|rowspan="5"|TBD
−
|A11
+
|rowspan="5"|TBD
−
|VDD_ANA_1V8
+
|rowspan="5"|TBD
−
|D
+
|rowspan="5"|TBD
−
|
+
|rowspan="5"|TBD
−
|
+
|Pin ALT-0
−
|
+
|TBD
 
|-
 
|-
−
|J1.108
+
|Pin ALT-1
−
|CSI_D0_P
+
|TBD
−
|CPU.MIPI_CSI1_D0_P
 
−
|B11
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.110
+
|Pin ALT-2
−
|CSI_D1_N
+
|TBD
−
|CPU.MIPI_CSI1_D1_N
 
−
|A10
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.112
+
|Pin ALT-3
−
|CSI_D1_P
+
|TBD
−
|CPU.MIPI_CSI1_D1_P
 
−
|B10
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.114
+
|Pin ALT-5
−
|USB1_RX_N
+
|TBD
−
|CPU.USB1_RX_N
 
−
|A12
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|Only for i.MX933x/i.MX935x
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.116
+
|rowspan="5"|J1.180
−
|USB1_RX_P
+
|rowspan="5"|TBD
−
|CPU.USB1_RX_P
+
|rowspan="5"|TBD
−
|B12
+
|rowspan="5"|TBD
−
|VDD_ANA_1V8
+
|rowspan="5"|TBD
−
|D
+
|rowspan="5"|TBD
−
|Only for i.MX933x/i.MX935x
+
|rowspan="5"|TBD
−
|
+
|Pin ALT-0
−
|
+
|TBD
 
|-
 
|-
−
|J1.118
+
|Pin ALT-1
−
|USB1_TX_N
+
|TBD
−
|CPU.USB1_TX_N
 
−
|A13
 
−
|VDD_ANA_1V8
 
−
|D
 
−
|Only for i.MX933x/i.MX935x
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.120
+
|Pin ALT-2
−
|USB1_TX_P
+
|TBD
−
|CPU.USB1_TX_P
+
|-
−
|B13
+
|Pin ALT-3
−
|VDD_ANA_1V8
+
|TBD
−
|D
 
−
|Only for i.MX933x/i.MX935x
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.122
+
|Pin ALT-5
−
|DGND
+
|TBD
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="6" |J1.124
+
|rowspan="5"|J1.182
−
| rowspan="6" |ENET1_MDC
+
|rowspan="5"|TBD
−
| rowspan="6" |CPU.ENET1_MDC
+
|rowspan="5"|TBD
−
| rowspan="6" |AA11
+
|rowspan="5"|TBD
−
| rowspan="6" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="6" |IO
+
|rowspan="5"|TBD
−
| rowspan="6" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|ENET_QOS_MDC
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|UART3_DCR_B
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|I3C2_SCL
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|USB1_OTG_ID
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO00
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO4_IO00
+
|TBD
 
|-
 
|-
−
| rowspan="6" |J1.126
+
|rowspan="5"|J1.184
−
| rowspan="6" |ENET1_MDIO
+
|rowspan="5"|TBD
−
| rowspan="6" |CPU.ENET1_MDIO
+
|rowspan="5"|TBD
−
| rowspan="6" |AA10
+
|rowspan="5"|TBD
−
| rowspan="6" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="6" |IO
+
|rowspan="5"|TBD
−
| rowspan="6" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|ENET_QOS_MDIO
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|UART3_RIN_B
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|I3C2_SDA
+
|TBD
 
|-
 
|-
 
|Pin ALT-3
 
|Pin ALT-3
−
|USB1_OTG_PWR
+
|TBD
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO01
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO4_IO01
+
|TBD
 
|-
 
|-
−
| rowspan="3" |J1.128
+
|rowspan="5"|J1.186
−
| rowspan="3" |SD1_CLK
+
|rowspan="5"|TBD
−
| rowspan="3" |CPU.SD1_CLK
+
|rowspan="5"|TBD
−
| rowspan="3" |Y11
+
|rowspan="5"|TBD
−
| rowspan="3" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="3" |IO
+
|rowspan="5"|TBD
−
| rowspan="3" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC1_CLK
+
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-3
−
|FLEXIO1_FLEXIO08
+
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO3_IO08
+
|TBD
 
|-
 
|-
−
| rowspan="3" |J1.130
+
|rowspan="5"|J1.188
−
| rowspan="3" |SD1_CMD
+
|rowspan="5"|TBD
−
| rowspan="3" |CPU.SD1_CMD
+
|rowspan="5"|TBD
−
| rowspan="3" |AA12
+
|rowspan="5"|TBD
−
| rowspan="3" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="3" |IO
+
|rowspan="5"|TBD
−
| rowspan="3" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC1_CMD
+
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-1
−
|FLEXIO1_FLEXIO09
+
|TBD
 
|-
 
|-
−
|Pin ALT-5
+
|Pin ALT-2
−
|GPIO3_IO09
+
|TBD
 
|-
 
|-
−
|J1.132
+
|Pin ALT-3
−
|ETH1_LED5
+
|TBD
−
|LAN.LED5/GPIO4
+
|-
−
|13
+
|Pin ALT-5
−
|NVCC_3V3
+
|TBD
−
|O
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="4" |J1.134
+
|rowspan="5"|J1.190
−
| rowspan="4" |SD1_STROBE
+
|rowspan="5"|TBD
−
| rowspan="4" |CPU.SD1_CLK
+
|rowspan="5"|TBD
−
| rowspan="4" |Y11
+
|rowspan="5"|TBD
−
| rowspan="4" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="4" |IO
+
|rowspan="5"|TBD
−
| rowspan="4" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC1_CLK
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|FLEXSPI1_A_DQS
+
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-3
−
|FLEXIO1_FLEXIO18
+
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO3_IO018
+
|TBD
−
|-
 
−
|J1.136
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="3" |J1.138
+
|rowspan="5"|J1.192
−
| rowspan="3" |SD1_DATA0
+
|rowspan="5"|TBD
−
| rowspan="3" |CPU.SD1_DATA0
+
|rowspan="5"|TBD
−
| rowspan="3" |AA14
+
|rowspan="5"|TBD
−
| rowspan="3" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="3" |IO
+
|rowspan="5"|TBD
−
| rowspan="3" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC1_DATA0
+
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-1
−
|FLEXIO1_FLEXIO10
+
|TBD
 
|-
 
|-
−
|Pin ALT-5
+
|Pin ALT-2
−
|GPIO3_IO10
+
|TBD
 
|-
 
|-
−
| rowspan="3" |J1.140
+
|Pin ALT-3
−
| rowspan="3" |SD1_DATA1
+
|TBD
−
| rowspan="3" |CPU.SD1_DATA1
 
−
| rowspan="3" |AA15
 
−
| rowspan="3" |NVCC_3V3
 
−
| rowspan="3" |IO
 
−
| rowspan="3" |
 
−
|Pin ALT-0
 
−
|USDHC1_DATA1
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO1_FLEXIO11
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO3_IO11
+
|TBD
 
|-
 
|-
−
| rowspan="3" |J1.142
+
|rowspan="5"|J1.194
−
| rowspan="3" |SD1_DATA2
+
|rowspan="5"|TBD
−
| rowspan="3" |CPU.SD1_DATA2
+
|rowspan="5"|TBD
−
| rowspan="3" |AA16
+
|rowspan="5"|TBD
−
| rowspan="3" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="3" |IO
+
|rowspan="5"|TBD
−
| rowspan="3" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC1_DATA2
+
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-1
−
|FLEXIO1_FLEXIO12
+
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO3_IO12
+
|TBD
 
|-
 
|-
−
| rowspan="3" |J1.144
+
|rowspan="5"|J1.196
−
| rowspan="3" |SD1_DATA3
+
|rowspan="5"|TBD
−
| rowspan="3" |CPU.SD1_DATA3
+
|rowspan="5"|TBD
−
| rowspan="3" |Y11
+
|rowspan="5"|TBD
−
| rowspan="3" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="3" |IO
+
|rowspan="5"|TBD
−
| rowspan="3" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC1_DATA3
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|FLEXSPI1_A_SS1_B
+
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-2
−
|FLEXIO1_FLEXIO13
+
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO3_IO13
+
|TBD
−
|-
 
−
|J1.146
 
−
|DGND
 
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="4" |J1.148
+
|rowspan="5"|J1.198
−
| rowspan="4" |SD1_DATA4
+
|rowspan="5"|TBD
−
| rowspan="4" |CPU.SD1_DATA4
+
|rowspan="5"|TBD
−
| rowspan="4" |Y13
+
|rowspan="5"|TBD
−
| rowspan="4" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="4" |IO
+
|rowspan="5"|TBD
−
| rowspan="4" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC1_DATA4
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|FLEXSPI1_A_DATA04
+
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-2
−
|FLEXIO1_FLEXIO14
+
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO3_IO14
+
|TBD
 
|-
 
|-
−
| rowspan="4" |J1.150
+
|rowspan="5"|J1.200
−
| rowspan="4" |SD1_DATA5
+
|rowspan="5"|TBD
−
| rowspan="4" |CPU.SD1_DATA5
+
|rowspan="5"|TBD
−
| rowspan="4" |Y14
+
|rowspan="5"|TBD
−
| rowspan="4" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="4" |IO
+
|rowspan="5"|TBD
−
| rowspan="4" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC1_DATA5
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|FLEXSPI1_A_DATA05
+
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-3
−
|FLEXIO1_FLEXIO15
+
|TBD
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO3_IO15
+
|TBD
 
|-
 
|-
−
| rowspan="4" |J1.152
+
|rowspan="5"|J1.202
−
| rowspan="4" |SD1_DATA5
+
|rowspan="5"|TBD
−
| rowspan="4" |CPU.SD1_DATA6
+
|rowspan="5"|TBD
−
| rowspan="4" |Y15
+
|rowspan="5"|TBD
−
| rowspan="4" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="4" |IO
+
|rowspan="5"|TBD
−
| rowspan="4" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|USDHC1_DATA6
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|FLEXSPI1_A_DATA06
+
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-2
−
|FLEXIO1_FLEXIO16
+
|TBD
 
|-
 
|-
−
|Pin ALT-5
+
|Pin ALT-3
−
|GPIO3_IO16
+
|TBD
−
|-
 
−
| rowspan="4" |J1.154
 
−
| rowspan="4" |SD1_DATA7
 
−
| rowspan="4" |CPU.SD1_DATA7
 
−
| rowspan="4" |Y16
 
−
| rowspan="4" |NVCC_3V3
 
−
| rowspan="4" |IO
 
−
| rowspan="4" |
 
−
|Pin ALT-0
 
−
|USDHC1_DATA7
 
−
|-
 
−
|Pin ALT-1
 
−
|FLEXSPI1_A_DATA07
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO1_FLEXIO17
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO3_IO17
 
−
|-
 
−
| rowspan="4" |J1.156
 
−
| rowspan="4" |ENET2_TD3
 
−
| rowspan="4" |CPU.ENET2_TD3
 
−
| rowspan="4" |T10
 
−
| rowspan="4" |NVCC_3V3
 
−
| rowspan="4" |IO
 
−
| rowspan="4" |
 
−
|Pin ALT-0
 
−
|ENET1_RGMII_TD3
 
−
|-
 
−
|Pin ALT-2
 
−
|SAI2_RX_DATA00
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO16
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO4_IO16
+
|TBD
 
|-
 
|-
−
| rowspan="5" |J1.158
+
|rowspan="5"|J1.204
−
| rowspan="5" |ENET2_TD2
+
|rowspan="5"|TBD
−
| rowspan="5" |CPU.ENET2_TD2
+
|rowspan="5"|TBD
−
| rowspan="5" |V8
+
|rowspan="5"|TBD
−
| rowspan="5" |NVCC_3V3
+
|rowspan="5"|TBD
−
| rowspan="5" |IO
+
|rowspan="5"|TBD
−
| rowspan="5" |
+
|rowspan="5"|TBD
 
|Pin ALT-0
 
|Pin ALT-0
−
|ENET1_RGMII_TD2
+
|TBD
 
|-
 
|-
 
|Pin ALT-1
 
|Pin ALT-1
−
|ENET1_TX_CLK // CCMSRCGPMCMIX.ENET_REF_CLK_ROOT
+
|TBD
 
|-
 
|-
 
|Pin ALT-2
 
|Pin ALT-2
−
|SAI2_RX_DATA01
+
|TBD
 
|-
 
|-
−
|Pin ALT-4
+
|Pin ALT-3
−
|FLEXIO2_FLEXIO17
+
|TBD
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO17
 
−
|-
 
−
| rowspan="5" |J1.160
 
−
| rowspan="5" |ENET2_TD1
 
−
| rowspan="5" |CPU.ENET2_TD1
 
−
| rowspan="5" |U8
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |IO
 
−
| rowspan="5" |
 
−
|Pin ALT-0
 
−
|ENET1_RGMII_TD1
 
−
|-
 
−
|Pin ALT-1
 
−
|UART4_RTS_B
 
−
|-
 
−
|Pin ALT-2
 
−
|SAI2_RX_DATA02
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO18
 
 
|-
 
|-
 
|Pin ALT-5
 
|Pin ALT-5
−
|GPIO4_IO18
+
|TBD
 
|-
 
|-
−
| rowspan="5" |J1.162
 
−
| rowspan="5" |ENET2_TD0
 
−
| rowspan="5" |CPU.ENET2_TD0
 
−
| rowspan="5" |T8
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |IO
 
−
| rowspan="5" |
 
−
|Pin ALT-0
 
−
|ENET1_RGMII_TD0
 
−
|-
 
−
|Pin ALT-1
 
−
|UART4_TX
 
−
|-
 
−
|Pin ALT-2
 
−
|SAI2_RX_DATA03
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO19
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO19
 
−
|-
 
−
|J1.164
 
−
|DGND
 
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="5" |J1.166
 
−
| rowspan="5" |ENET2_TXC
 
−
| rowspan="5" |CPU.ENET2_TXC
 
−
| rowspan="5" |U6
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |IO
 
−
| rowspan="5" |
 
−
|Pin ALT-0
 
−
|ENET1_RGMI_TXC
 
−
|-
 
−
|Pin ALT-1
 
−
|ENET1_TX_ER
 
−
|-
 
−
|Pin ALT-2
 
−
|SAI2_TX_BCLK
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO21
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO21
 
−
|-
 
−
| rowspan="5" |J1.168
 
−
| rowspan="5" |ENET2_TX_CTL
 
−
| rowspan="5" |CPU.ENET2_TX_CTL
 
−
| rowspan="5" |V6
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |IO
 
−
| rowspan="5" |
 
−
|Pin ALT-0
 
−
|ENET1_RGMI_TX_CTL
 
−
|-
 
−
|Pin ALT-1
 
−
|UART4_DTR_B
 
−
|-
 
−
|Pin ALT-2
 
−
|SAI2_TX_SYNC
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO20
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO20
 
−
|-
 
−
| rowspan="5" |J1.170
 
−
| rowspan="5" |ENET2_MDC
 
−
| rowspan="5" |CPU.ENET2_MDC
 
−
| rowspan="5" |Y7
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |IO
 
−
| rowspan="5" |
 
−
|Pin ALT-0
 
−
|ENET1_MDC
 
−
|-
 
−
|Pin ALT-1
 
−
|UART4_DCR_B
 
−
|-
 
−
|Pin ALT-2
 
−
|SAI2_RX_SYNC
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO14
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO14
 
−
|-
 
−
| rowspan="5" |J1.172
 
−
| rowspan="5" |ENET2_MDIO
 
−
| rowspan="5" |CPU.ENET2_MDIO
 
−
| rowspan="5" |AA6
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |IO
 
−
| rowspan="5" |
 
−
|Pin ALT-0
 
−
|ENET1_MDIO
 
−
|-
 
−
|Pin ALT-1
 
−
|UART4_RIN_B
 
−
|-
 
−
|Pin ALT-2
 
−
|SAI2_RX_BCLK
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO15
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO15
 
−
|-
 
−
| rowspan="5" |J1.174
 
−
| rowspan="5" |ENET2_RX_CTL
 
−
| rowspan="5" |CPU.ENET2_RX_CTL
 
−
| rowspan="5" |Y4
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |IO
 
−
| rowspan="5" |
 
−
|Pin ALT-0
 
−
|ENET1_RGMII_RX_CTL
 
−
|-
 
−
|Pin ALT-1
 
−
|UART4_DSR_B
 
−
|-
 
−
|Pin ALT-2
 
−
|SAI2_TX_DATA00
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO22
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO22
 
−
|-
 
−
| rowspan="5" |J1.176
 
−
| rowspan="5" |ENET2_RD0
 
−
| rowspan="5" |CPU.ENET2_RD0
 
−
| rowspan="5" |AA4
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |IO
 
−
| rowspan="5" |
 
−
|Pin ALT-0
 
−
|ENET1_RGMII_RD0
 
−
|-
 
−
|Pin ALT-1
 
−
|UART4_RX
 
−
|-
 
−
|Pin ALT-2
 
−
|SAI2_TX_DATA02
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO24
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO24
 
−
|-
 
−
| rowspan="5" |J1.178
 
−
| rowspan="5" |ENET2_RD1
 
−
| rowspan="5" |CPU.ENET2_RD1
 
−
| rowspan="5" |Y5
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |IO
 
−
| rowspan="5" |
 
−
|Pin ALT-0
 
−
|ENET1_RGMII_RD1
 
−
|-
 
−
|Pin ALT-1
 
−
|SPDIF_IN
 
−
|-
 
−
|Pin ALT-2
 
−
|SAI2_TX_DATA03
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO25
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO25
 
−
|-
 
−
| rowspan="6" |J1.180
 
−
| rowspan="6" |ENET2_RD2
 
−
| rowspan="6" |CPU.ENET2_RD2
 
−
| rowspan="6" |AA5
 
−
| rowspan="6" |NVCC_3V3
 
−
| rowspan="6" |IO
 
−
| rowspan="6" |
 
−
|Pin ALT-0
 
−
|ENET1_RGMII_RD2
 
−
|-
 
−
|Pin ALT-1
 
−
|UART4_CTS_B
 
−
|-
 
−
|Pin ALT-2
 
−
|SAI2_MCLK
 
−
|-
 
−
|Pin ALT-3
 
−
|MQS2_RIGHT
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO26
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO26
 
−
|-
 
−
| rowspan="6" |J1.182
 
−
| rowspan="6" |ENET2_RD3
 
−
| rowspan="6" |CPU.ENET2_RD3
 
−
| rowspan="6" |Y6
 
−
| rowspan="6" |NVCC_3V3
 
−
| rowspan="6" |IO
 
−
| rowspan="6" |
 
−
|Pin ALT-0
 
−
|ENET1_RGMII_RD3
 
−
|-
 
−
|Pin ALT-1
 
−
|SPDIF_OUT
 
−
|-
 
−
|Pin ALT-2
 
−
|SPDIF_IN
 
−
|-
 
−
|Pin ALT-3
 
−
|MQS2_LEFT
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO27
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO27
 
−
|-
 
−
| rowspan="5" |J1.184
 
−
| rowspan="5" |ENET2_RXC
 
−
| rowspan="5" |CPU.ENET2_RXC
 
−
| rowspan="5" |AA3
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |IO
 
−
| rowspan="5" |
 
−
|Pin ALT-0
 
−
|ENET1_RGMII_RXC
 
−
|-
 
−
|Pin ALT-1
 
−
|ENET1_RX_ER
 
−
|-
 
−
|Pin ALT-2
 
−
|SAI2_TX_DATA01
 
−
|-
 
−
|Pin ALT-4
 
−
|FLEXIO2_FLEXIO23
 
−
|-
 
−
|Pin ALT-5
 
−
|GPIO4_IO23
 
−
|-
 
−
|J1.186
 
−
|USB1_VBUS
 
−
|CPU.USB1_VBUS
 
−
|F13
 
−
|NVCC_3V3
 
−
|D
 
−
|(3V3 reference signal)
 
−
|
 
−
|
 
−
|-
 
−
|J1.188
 
−
|USB2_VBUS
 
−
|CPU.USB2_VBUS
 
−
|E14
 
−
|NVCC_3V3
 
−
|D
 
−
|(3V3 reference signal)
 
−
|
 
−
|
 
−
|-
 
−
|J1.190
 
−
|DGND
 
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.192
 
−
|USB1_ID
 
−
|CPU.USB1_ID
 
−
|C11
 
−
|
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.194
 
−
|USB2_ID
 
−
|CPU.USB2_ID
 
−
|E12
 
−
|
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.196
 
−
|USB1_DN
 
−
|CPU.USB1_DN
 
−
|A14
 
−
|
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.198
 
−
|USB1_DP
 
−
|CPU.USB1_DP
 
−
|B14
 
−
|
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.200
 
−
|USB2_DP
 
−
|CPU.USB2_DP
 
−
|B15
 
−
|
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.202
 
−
|USB2_DN
 
−
|CPU.USB2_DN
 
−
|A15
 
−
|
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.204
 
−
|DGND
 
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
 
|}
 
|}
  

Revision as of 13:01, 15 May 2023

HOME SOMs SBCs ToloMEO Embedded Assistant Sale-tag.pngGET A QUOTE Customer-service.pngONLINE HELPDESK
Roadmap IoT Services ML/AI services Embedded Design Services
History
ID# Issue Date Notes

17891

15/05/2023 Preliminary version


Connectors and Pinout Table[edit | edit source]

Connectors description[edit | edit source]

In the following table are described all available connectors integrated on AURA SOM:

Connector name Connector Type Notes Carrier board counterpart
J1 SODIMM DDR3 edge connector 204 pin TE Connectivity 2013289-1

The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to ORCA pinout specifications. See the images below for reference:

AURA TOP view
AURA BOTTOM view

Pinout table naming conventions[edit | edit source]

This chapter contains the pinout description of the AURA module, grouped in two tables (odd and even pins) that report the pin mapping of the TBD: connector type AURA connector.

Each row in the pinout tables contains the following information:

Pin Reference to the connector pin
Pin Name Pin (signal) name on the AURA connectors
Internal
connections 		Connections to the AURA components
  • CPU.<x> : pin connected to CPU pad named <x>
  • CAN.<x> : pin connected to the CAN transceiver (TI SN65HVD232)
  • PMIC.<x> : pin connected to the Power Manager IC (NXP PCA9451A)
  • LAN.<x> : pin connected to the LAN PHY (Microchip LAN8830T-V)
  • NOR.<x>: pin connected to the flash NOR
  • SV.<x>: pin connected to voltage supervisor
  • MTR: pin connected to voltage monitors
Ball/pin # Component ball/pin number connected to signal
Voltage I/O voltage levels
Type Pin type:
  • I = Input
  • O = Output
  • D = Differential
  • Z = High impedance
  • S = Power supply voltage
  • G = Ground
  • A = Analog signal
Notes Remarks on special pin characteristics
Pin MUX alternative functions Muxes:
  • Pin ALT-0
  • ...
  • Pin ALT-N

The number of functions depends on platform

Voltage domains[edit | edit source]

Voltage domain Nominal voltage [V] Notes
3.3VIN 3.3 See Operational_characteristics of the SoM wiki page
VCC_ENET_1V8 1.8 Voltage generated by the internal PSU. See Power Supply Unit (PSU) wiki page
IO_3V3 3.3 Voltage generated by the internal PSU. See Power Supply Unit (PSU) wiki page
GEN_2V5 2.5 Voltage generated by the internal PSU. See Power Supply Unit (PSU) wiki page

Pinout Table ODD pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage

domain

Type Notes Alternative Functions
J1.1 DGND DGND - - G
J1.3 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.5 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.7 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.9 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.11 DGND DGND - - G
J1.13 ETH1_LED1 LAN.LED1/PME_N1 18 NVCC_3V3 O
J1.15 ETH1_LED2 LAN.LED2 16 NVCC_3V3 O
J1.17 DGND DGND - - G
J1.19 ETH1_TXRX0_P LAN.TXRXP_A 2 NVCC_3V3 D
J1.21 ETH1_TXRX0_M LAN.TXRXM_A 3 NVCC_3V3 D
J1.23 ETH1_TXRX1_P LAN.TXRXP_B 5 NVCC_3V3 D
J1.25 ETH1_TXRX1_M LAN.TXRXM_B 6 NVCC_3V3 D
J1.27 ETH1_TXRX2_P LAN.TXRXP_C 7 NVCC_3V3 D
J1.29 ETH1_TXRX2_M LAN.TXRXM_C 8 NVCC_3V3 D
J1.31 ETH1_TXRX3_P LAN.TXRXP_D 10 NVCC_3V3 D
J1.33 ETH1_TXRX3_M LAN.TXRXM_D 11 NVCC_3V3 D
J1.35 DGND DGND - - G
J1.37 ETH1_LED3 LAN.LED3/GPIO2 15 NVCC_3V3 O
J1.39 ETH1_LED4 LAN.LED4/GPIO3 14 NVCC_3V3 O
J1.41 ETH_OSC_EN 46 NVCC_3V3 I (mounting option)
J1.43 GPIO_IO06 CPU.GPIO_IO06 L20 NVCC_GPIO IO Pin ALT-0 GPIO2_IO06
Pin ALT-1 TMP5_CH0
Pin ALT-2 PDM.BIT_STREAM[1]
Pin ALT-3 LCDIF.D[2]
Pin ALT-4 SPI7.SOUT
Pin ALT-5 UART6.CTS_B
Pin ALT-6 I2C7.SDA
Pin ALT-7 FLEXIO1.FLEXIO[6]

Pinout Table EVEN pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage domain Type Notes Alternative Functions
J1.2 SD2_CMD CPU.SD2_CMD F19 AXEL_IO_3V3 IO Notes Pin ALT-0 SD2_CMD
Pin ALT-1 ECSPI5_MOSI
Pin ALT-2 KEY_ROW5
Pin ALT-3 AUD4_RXC
Pin ALT-5 GPIO1_IO11
J1.4 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.6 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.8 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.10 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.12 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.14 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.16 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.18 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.20 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.22 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.24 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.26 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.28 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.30 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.32 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.34 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.36 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.38 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.40 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.42 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.44 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.46 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.48 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.50 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.52 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.54 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.56 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.58 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.60 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.62 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.64 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.66 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.68 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.70 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.72 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.74 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.76 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.78 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.80 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.82 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.84 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.86 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.88 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.90 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.92 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.94 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.96 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.98 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.100 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.102 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.104 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.106 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.108 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.110 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.112 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.114 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.116 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.118 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.120 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.122 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.124 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.126 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.128 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.130 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.132 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.134 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.136 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.138 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.140 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.142 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.144 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.146 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.148 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.150 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.152 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.154 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.156 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.158 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.160 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.162 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.164 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.166 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.168 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.170 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.172 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.174 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.176 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.178 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.180 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.182 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.184 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.186 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.188 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.190 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.192 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.194 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.196 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.198 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.200 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.202 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.204 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
HOME SOMs SBCs ToloMEO Embedded Assistant Sale-tag.pngGET A QUOTE Customer-service.pngONLINE HELPDESK
Roadmap IoT Services ML/AI services Embedded Design Services
Retrieved from "https://wiki.dave.eu/index.php?title=AURA_SOM/AURA_Hardware/Pinout_Table&oldid=17894"