Difference between revisions of "Reset scheme (Naon)"

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==Accessible reset signals==
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Five different signals are provided by Naon SOM. FOllowing sections describes in more detail each one.
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Five different signals are provided by Naon SOM. Following sections describe in more detail each one.
 
 
===MRST (J2.102)===
 
===MRST (J2.102)===
 
This pin is connected to HDRST signal (cold reset) of [http://www.ti.com/product/tps659113 PMIC TPS659113]. When high, this signals keeps PMIC in off mode and resets TPS659113 to default settings. MRST has a weak internal pulldown.
 
This pin is connected to HDRST signal (cold reset) of [http://www.ti.com/product/tps659113 PMIC TPS659113]. When high, this signals keeps PMIC in off mode and resets TPS659113 to default settings. MRST has a weak internal pulldown.
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===PORSTn (J2.109)===
 
===PORSTn (J2.109)===
 
PORSTn is a bidirectional open-drain signal. It is connected to:
 
PORSTn is a bidirectional open-drain signal. It is connected to:
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* PORn input (Power-on Reset) of DM8148 processor
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*
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* output of voltage monitor (see [[Reset scheme (Naon)#Voltage monitor]])
 
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* NRESPWRON2 output of PMIC.
 
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Internal pullup is 10kOhm.
 
  
 
===RSTOUTn (J2.91)===
 
===RSTOUTn (J2.91)===
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This ouput signal is asserted by DM8148 processor until it gets out of reset. It is usually used to reset external memories and peripherals conneteced to processor. It is connected to:
 
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* RSTOUT_WD_OUTn pad of DM8148 processor
 
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* 2k2 pull down resistor
 
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* peripherals and memories.
 
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In case it is used to reset devices on carrier board, its driving capability has to be taken into account.
 
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===CPU_RESETn (J2.15)===
 
===CPU_RESETn (J2.15)===
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This input signal acts as External Warm Reset. It is connected to processor's RESETn pad. Internal pullup is 2.2kOhm.
 
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===JTAG_TRSTn (J2.100)===
 
===JTAG_TRSTn (J2.100)===
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This input signal acts as Emulation Warm Reset. It is connected to processor's TRSTn pad. Internal pulldown is 4.7kOhm
 
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==Voltage monitor==
 
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Naon SOM is equipped with a multiple-input voltage monitor whose reset output is connected to PORSTn. Monitored voltage rails include 3.3V provided by carrier board.
 

Revision as of 12:57, 2 May 2012

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Naon am387x-dm814x.png Applies to Naon

Five different signals are provided by Naon SOM. FOllowing sections describes in more detail each one.

MRST (J2.102)[edit | edit source]

This pin is connected to HDRST signal (cold reset) of PMIC TPS659113. When high, this signals keeps PMIC in off mode and resets TPS659113 to default settings. MRST has a weak internal pulldown.

PORSTn (J2.109)[edit | edit source]

PORSTn is a bidirectional open-drain signal. It is connected to:

RSTOUTn (J2.91)[edit | edit source]

CPU_RESETn (J2.15)[edit | edit source]

JTAG_TRSTn (J2.100)[edit | edit source]

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