Difference between revisions of "AXEL Lite SOM/AXEL Lite Hardware/Peripherals/MIPI"

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<section end=History/>
 
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__FORCETOC__
 
 
<section begin=Body/>
 
<section begin=Body/>
  
 
==Peripheral MIPI ==
 
==Peripheral MIPI ==
  
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The CSI-2 Host Controller is a digital core that implements all protocol functions defined in the MIPI CSI-2 Specification, providing an interface between the System and the MIPI
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''TBD: sostituire le sezioni con le informazioni sull'uso della periferica''
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D-PHY, allowing the communication with a MIPI CSI-2 compliant Camera Sensor
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''Nell'esempio di seguito c'è la descrizione dell'interfaccia HDMI''
  
 
=== Description  ===
 
=== Description  ===
  
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The MIPI interface available on AXEL Lite is based on i.MX6 SoC and support the following features:
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The MIPI interface available on AXEL Lite is based on i.MX6 SoC.  
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* Compliant with MIPI Alliance Standard for Camera Serial Interface 2 (CSI-2), Version 1.00 - 29 November 2005
 
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* Interface with MIPI D-PHY following PHY Protocol Interface (PPI), as defined in MIPI Alliance Specification for D-PHY, Version 1.00.00 - 14 May 2009
 
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* Supports up to 2 (S/DL) and 4 (D/Q) D-PHY Rx Data Lanes
 
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* Dynamically configurable multi-lane merging
 
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* Long and Short packet decoding
 
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* Timing accurate signaling of Frame and Line synchronization packets
 
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* Support for several frame formats such as:
 
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** General Frame or Digital Interlaced Video with or without accurate sync timing
 
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** Data type (Packet or Frame level) and Virtual Channel interleaving
 
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* 32-bit Image Data Interface delivering data formatted as recommended in CSI-2 Specification
 
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* Supports all primary and secondary data formats:
 
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** RGB, YUV and RAW color space definitions
 
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** From 24-bit down to 6-bit per pixel
 
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** Generic or user-defined byte-based data types
 
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* Error detection and correction: PHY, Packet, Line, Frame
 
  
 
=== Camera ports ===
 
=== Camera ports ===

Revision as of 14:06, 7 October 2020

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History
Version Issue Date Notes
X.Y.Z Month Year TBD
[TBD_link X.Y.Z] Month Year TBD
... ... ...


Peripheral MIPI[edit | edit source]

TBD: sostituire le sezioni con le informazioni sull'uso della periferica Nell'esempio di seguito c'è la descrizione dell'interfaccia HDMI

Description[edit | edit source]

The MIPI interface available on AXEL Lite is based on i.MX6 SoC.

Camera ports[edit | edit source]

The MIPI CSI-2 Serial port supports the following standards and features:

i.MX 6Solo/6DualLite[edit | edit source]

  • Supporting from 80 Mbps to 1 Gbps speed per data lane
  • CSI-2 Receiver core can manage one clock lane and up to two lanes

i.MX 6Dual/6Quad[edit | edit source]

  • Support up to 1Gbps per lane in 1/2/3-lane mode and up to 800 Mbps/lane in 4-lane mode
  • CSI-2 Receiver core can manage one clock lane and up to four data lanes

Pin mapping[edit | edit source]

The Pin mapping is described in the Pinout table section

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