ZERO SOM/ZERO Hardware/Power and Reset/System boot
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System boot[edit | edit source]
The boot process begins at SOM reset, where the hardware reset logic forces the ARM core to begin execution starting from the on-chip boot ROM. The boot ROM:
- determines whether the boot is secure or non-secure
- performs some initialization of the system and clean-ups
- reads the mode pins to determine the primary boot device
- once it is satisfied, it executes the boot code
Boot options[edit | edit source]
By default, ZERO SoM boots from on-board eMMC storage device. However, bringing low FORCE_RECOVERY# ball T17, Zero SOM boots from USB.
Other options are available on-demand, however, allowing implementation of different configurations. DAVE Embedded Systems' team is available for additional information on this matter. If necessary, please contact sales@dave.eu.
Boot modes[edit | edit source]
The OSM standard provides three contacts for configuring boot modes. The following table shows the preconfigured boot modes:
| Ball | OSM name | Ball | OSM name | Ball | OSM name | Boot mode | Peripheral / bus |
|---|---|---|---|---|---|---|---|
| T17 | FORCE_RECOVERY# | U19 | BOOT_SEL0# | R18 | BOOT_SEL1# | ||
| LOW | x | HIGH | USB boot | OSM USB_A | |||
| LOW | eMMC boot mode (3.3V) on SDHI0 | no standard OSM mapping | |||||
| HIGH | HIGH | HIGH | eSD boot mode (3.3V) on SDHI1 | eMMC on SoM | |||
| HIGH | LOW | xSPI0 boot mode (x8 boot serial flash) | no standard OSM mapping | ||||
| LOW | HIGH | xSPI1 boot mode (x1 boot serial flash) | no standard OSM mapping | ||||
| LOW | LOW | xSPI0 boot mode (x1 boot serial flash) | OSM SPI_A | ||||
Electrically these contacts are open drain inputs with 10 kΩ pull-up on SoM referred to 1.8 V.
In any case, the boot process is managed by on-chip boot ROM code which is described in detail in the processor's Reference Manual.
Note on boot signals[edit | edit source]
The boot mode is defined by the values of certain pins (MD0, MD1, MD2, MDW0, MDW1, MDV, MDD), sampled when the reset signal is deactivated.
After reset, the SoC uses these setting pins for other functionality, especially for ETH_A_TXD0, ETH_B_TXD0, ETH_B_TXD1, ETH_B_TXD2, ETH_B_TXD3, ETH_B_TXEN and GPIO_A_2 OSM signals.
To allow proper sampling of the bootstrap pins, the SoM circuitry sets the involved OSM signals into high impedance as long as signal RESET_OUT# (ball Y14) is low.
