ZERO SOM/ZERO Hardware/Power and Reset/Reset scheme and control signals
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| 2026/06/16 | First version | ||
Reset scheme and control signals[edit | edit source]
The following picture shows the simplified block diagram of reset scheme and voltage monitoring.
- MRST
- POR
- SNVS
- SYSRST
- ...
CPU_PORn[edit | edit source]
The following devices can assert this active-low signal:
- PMIC
- multiple-voltage monitor: this device monitors critical power voltages and triggers a reset pulse in case any of these exhibits a brownout condition
Since SPI NOR flash can be used as boot device, CPU_PORn is connected to this device too. This guarantees it is in a known state when reset signal is released.
Handling CPU-initiated software reset[edit | edit source]
By default, RZ/T2H processor does not assert any external signal when it initiates a software reset sequence. Also default software reset implementation does not guarantee that all processor registers are reset properly.
For these reasons, it is strongly recommended to use a different approach that, in combination with the use of a processor's watchdog timer (WDT), provides a full hardware reset in case a software reset is issued.
This technique is implemented in DESK-RZ-L. At software level, U-Boot and Linux kernel software reset routines make use of processor's WDT #2 to assert the WDOG2_B reset signal. This signal in turn is routed to GPIO_1 pad (MUX mode = 1).
