ZERO SOM/ZERO Hardware/Power and Reset/Reset scheme and control signals

History
Issue Date	Notes
2025/07/30	First documentation release

Reset scheme and control signals

The following picture shows the simplified block diagram of reset scheme and voltage monitoring circuitry:

The reset sources are described below:

• External source:
  • PWR_BTN# driven low for at least 150 ms causes a cold reset i.e. turns off all onboard SoM power rails and restarts a power-up sequence.
  • RESET_IN# is the first of three warm reset sources: the RESET_OUT# warm reset signal (obtained as an AND of the three warm reset sources) is sent to the SoC, the memories on SoM and the carrier.
• Inside the SoM:
  • SEQ_RST#, the second warm reset source, it is released when the power-on sequence is completed, after about 100 ms from the release of PWR_BTN#. This signal is not carried to the SoM contacts.
  • PWR_GOOD, the third warm reset source, it is released when all PWR_GOOD of the four DC-DCs on SoM are valid. The signal is output on carrier as a monitor. In particular the SoM ANDs the different PWR_GOODs, condition that ensures all regulators on SoM are active and their output voltages within tolerances. It is possible to externally monitor the four voltage regulators individually: DAVE Embedded Systems' team is available for additional information by contact [[1]].

• Output signals:
  • RESET_OUT# is obtained as an AND of the three warm reset sources; use this signal on carrier to reset the peripherals connected to the SoM. The SoM generates this signal, which is also sent internally to the SoC and memories.
  • SOC_RSTOUT# is generated by the SoC: it remains low for 450 μs in the event of SoC input reset, software reset or SoC error reset. For more details see RZ/T2H user's manual ch.6.4.9 and ch.6.5.2. This signal is a warm reset because it does not propagate internally to the SoM and therefore does not cause a power cycle. For example, to force a cold reset when a software reset occurs, a circuit must be provided on the carrier board.

CARRIER_PWR_EN signal is used to synchronise the switching of the voltages on the carrier: see Power_Supply_Unit_(PSU)_and_recommended_power-up_sequence section.

I/O ports after reset

After a reset, the SoC configures its ports that support the muxing of alternative functions to general I/O as Hi-Z, with the exception of signals P08_1 to P08_5 that are set as JTAG (TMS, TDI, TDO and TCK) and RSTOUT#.

For more details see RZ/T2H user's manual ch.17.

OSM contacts

The following table lists the contacts of ZERO SoM relating to the power circuit:

OSM contact	OSM name	Purpose	Required
AA9	PWR_BTN#	Input open-drain 5 V, pull-up on SoM
U17	RESET_IN#	Input open-drain 1.8 V, pull-up on SoM	Yes
V17	CARRIER_PWR_EN	Output CMOS 1.8 V	Yes
Y14	RESET_OUT#	Output CMOS 1.8 V	Yes
P16	SOC_RSTOUT#	Output CMOS 3.3 V
AL33	Vendor Defined	Output open-drain 5 V, PWR_GOOD (all DC-DCs)
AL33	Vendor Defined	Output open-drain 5 V, 3.3 V power good (optional)
AK32	Vendor Defined	Output open-drain 5 V, 1.8 V power good (optional)
AK33	Vendor Defined	Output open-drain 5 V, 1.1 V power good (optional)
AL32	Vendor Defined	Output open-drain 5 V, 0.8 V power good (optional)