ZERO SOM/ZERO Hardware/Peripherals/PCIe
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| 2025/06/12 | First release | ||
Peripheral PCIe[edit | edit source]
The PCI Express 3.0 Interface (PCIE) in the ZERO SOM can operate as a root complex or endpoint device.
Description[edit | edit source]
The PCIe module is compliant to the PCI Express Base Specification 3.1 and it has the following features:
- PCI Express Gen1 (2.5 [GT/s]) / Gen2 (5.0 [GT/s]) / Gen3 (8.0 [GT/s])
- Lane/Port: 1 lane × 2 ports (with common or separate reference clock) or 2 lanes × 1 port selectable
- Polarity inversion
- Maximum data payload of 256 bytes, Maximum read request size 512 bytes
- Number of outstanding 1-8
- Dynamic control of speed/width up/down configuration
- Power Management (not support ASPM L1-Substate)
- Error handling/logging (AER Support)
- Replay FIFO with ECC
- Module-stop state support to reduce power consumption
