ZERO SOM/ZERO Hardware/Peripherals/ADC

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History
Issue Date Notes
2025/06/12 First release


Peripheral ADC[edit | edit source]

The RZ/T2H SoC in the ZERO SOM has three units of a 12-bit A/D converter.

Description[edit | edit source]

The ADC12 module has the following features:

  • 3 units: unit 0, 1 (4 channels in LLPP of Cortex-R52), unit 2 (15 channels in NONSAFETY)
  • 12-bit digital value through successive approximation
  • Three ways to start A/D conversion: Software trigger, timer (MTU3, ELC) trigger, external trigger
  • Conversion time: 0.32 µs per channel
  • Operating mode: Scan mode (single scan mode, continuous scan mode, or 3 group scan mode) and Group priority control
  • Sample-and-hold function: Common sample-and-hold circuit included. In addition, channel-dedicated sample-and-hold function (3 channels: in all units) included
  • Sampling time can be set up for each channel
  • Double trigger mode (A/D conversion data duplicated)
  • Event linking by the ELC