Video input ports (Maya)

Info Box Applies to Maya

Overview

DM8148 processor provides a rich video subsystem that integrates input ports. These are described in detail on chapter 12 of [1] Technical Reference Manual.

Three video inputs are available:

• VIN0 (in turn splittable in two subports)
• VIN1 (in turn splittable in two subports)
• camera parallel interface (CPI).

From the architectural standpoint, VIN0 and VIN1 ports belong to the HDVPSS subsytems. For the sake of completeness a simplified block diagram of it is shown below.

Camera parallel interface belongs to the Imaging Subsystem (ISS) instead. As ISS documentation is released under NDA, no information are provided here. For more details about it please contact your local Texas Instruments sales representative or FAE.

Main features

The following is a list of VIN0/VIN1 main features:

• The HDVPSS supports two independently configurable external video input capture ports with up to 165MHz.
• Each video input capture port can be operated as one 24-bit mode to support RGB capture or 16-bit input channel (with separate Y and Cb/Cr inputs) or two clock independent 8-bit input channels (with interleaved Y/C data input).
• Support both embedded sync and discrete sync
• The video capture port channel supports de-multiplexing of both pixel-to-pixel and line-to-line multiplexed streams.
• Up to 1920x1200@60 Hz (165 MHz) input data rate supports 16-bit mode input port.
• Each video capture port supports one scaler capable of both up and down scaling of one non-multiplexed input stream (one of two 8-bit channel inputs or 16-bit channel input data). Note that if the source is from external video decoder/camera, only down scaling is supported.
• Each video capture port supports one programmable color space conversion to convert between 24-bit RGB data and YCbCr data.
• The VIP supports data storage in RGB, 422, and 420 formats.
• Each video capture port channel supports chroma down-sampling (422 to 420) for any non-multiplexed input data. The chroma down-sampling for multiplexed streams is done as memory to memory operations outside of HDVPSS on an individual frame data.

Routing on Maya connectors

The following tables lists which signals - referred to video input/output ports - are routed to Maya SODIMM connector and thus are available to user application. It is also useful to visualize potential issues due to the pads' multiplexing scheme.

PAD	VIN0	CPI	VIN1	VOUT0	VOUT1	VOUT1 (HDMI)	TV_OUT	Available on Maya connector (SODIMM pin #)
AE17	B_CLK							Y (152)
AB20	A_CLK							Y (155)
AC16	A_D23	D15						N
AC21	A_D22	D14						N
AE18	A_D21	D13						N
AC17	A_D20	D12						N
AF21	A_D19	D11						N
AF20	A_D18	D10						N
AB21	A_D17	D9						N
AA21	A_D16	D8						N
AC14	A_D15_BD7	SHUTTER						Y (149)
AC12	A_D14_BD6	STROBE						Y (147)
AF17	A_D13_BD5	RESET						Y (145)
AG17	A_D12_BD4							Y (143)
AH17	A_D11_BD3	WE						Y (141)
AH9	A_D10_BD2							Y (137)
AG9	A_D9_BD1							Y (135)
AB15	A_D8_BD0							Y (133)
AA11	A_D7							Y (131)
AH16	A_D6							Y (129)
AG16	A_D5							Y (127)
AH8	A_D4							Y (125)
AE12	A_D3							Y (123)
AC9	A_D2							Y (119)
AB11	A_D1							Y (117)
AF9	A_D0							Y (115)
AE21	A_DE / B_HSYNC							Y (148)
AC20	A_HSYNC							Y (161)
AA20	A_FLD / B_VSYNC							Y (146)
AD20	A_VSYNC							Y (159)
AD17	B_FLD	D4						Y (154)
AC22	A_FLD	D5						Y (151)
AC15	B_DE	D6						Y (156)
AB17	A_DE	D7						Y (153)
AF18		PCLK						Y (69)
AD18		D3			G_Y_YC[1]			N
AC18		D2			G_Y_YC[0]			N
AC19		D1			R_CR[1]			N
AA22		D0			R_CR[0]			N
AE23		HS			B_CB_C[1]			N
AD23		VS			B_CB_C[0]			N
AB23		WE / FLD			FLD			Y (105)
P26			B_CLK		AVID			N
Y22			A_CLK					N
AE27			A_D23		R_CR[2]	HPDET		N
AG28			A_D22		R_CR[3]	SDA		N
AF27			A_D21		G_Y_YC[2]	SCL		N
Y24			A_D20		R_CR[9]			N
W23			A_D19		R_CR[8]			N
V22			A_D18		R_CR[7]			N
AA25			A_D17		R_CR[6]			N
AC26			A_D16		R_CR[5]			N
AG27			A_D15		R_CR[4]			N
AD26			A_D14		G_Y_YC[9]			N
AE26			A_D13		G_Y_YC[8]			N
AF26			A_D12		G_Y_YC[7]			N
AH27			A_D11		G_Y_YC[6]			N
AG26			A_D10		G_Y_YC[5]			N
W22			A_D9		G_Y_YC[4]			N
Y23			A_D8		G_Y_YC[3]			N
AF28			A_D7		B_CB_C[2]	CEC		N
AA24			A_D6		B_CB_C[9]			N
AH26			A_D5		B_CB_C[8]			N
AC25			A_D4		B_CB_C[7]			N
AD25			A_D3		B_CB_C[6]			N
AF25			A_D2		B_CB_C[5]			N
AG25			A_D1		B_CB_C[4]			N
AH25			A_D0		B_CB_C[3]			N
R23			B_D7					N
P23			B_D6					N
G28			B_D5					N
H27			B_D4					N
J26			B_D3					N
R25			B_D2					N
L23			B_D1					N
L24			B_D0					N
AE24			A_HSYNC		CLK			N
AC24			A_VSYNC		HSYNC			N
AA23			A_DE / A_FLD		VSYNC			N
AD12				CLK				Y (61)
AF14				G_Y_YC[9]				Y (80)
AE14				G_Y_YC[8]				Y (78)
AD14				G_Y_YC[7]				Y (76)
AA8				G_Y_YC[6]				Y (74)
AB12				G_Y_YC[5]				Y (72)
AB8				G_Y_YC[4]				Y (70)
AH15				G_Y_YC[3]				Y (68)
AH7				G_Y_YC[2]				Y (66)
AG15				B_CB_C[9]				Y (62)
AF15				B_CB_C[8]				Y (60)
AB10				B_CB_C[7]				Y (58)
AC10				B_CB_C[6]				Y (56)
AD15				B_CB_C[5]				Y (54)
AD11				B_CB_C[4]				Y (52)
AE15				B_CB_C[3]				Y (50)
AG7				B_CB_C[2]				Y (48)
AC13				R_CR[9]				Y (87)
AE8				R_CR[8]				Y (85)
AF12				R_CR[7]				Y (83)
AF6				R_CR[6]				Y (81)
AF8				R_CR[5]				Y (79)
AA9				R_CR[4]				Y (77)
AB9				R_CR[3]				Y (75)
AD9				R_CR[2]				Y (73)
AB13				VSYNC				Y (65)
AC11				HSYNC				Y (63)
AF18				FLD				Y (69)
AA10				FLD/AVID				Y (67)
AG18						CLKP		N
AH18						CLKN		N
AH21						DN2		N
AG21						DP2		N
AH20						DN1		N
AG20						DP1		N
AH19						DN0		N
AG19						DP0		N
AF24						SCL		Y (165)
AG24						SDA		Y (167)
AB27						CEC		N
AA26						HPDET		N
AH24							OUT0	Y (18)
AH22							OUT1	n

Following is a brief summary of video input ports available on Maya connector:

• VIN0A: available (16/8-bit only)
• VIN0B: not available
• VIN1A: not available