Bureaucrats, dave_user, Administrators
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__FORCETOC__
{{WarningMessage|text=This technical note was validated against specific versions of hardware and software. What is described here may not work with other versions.}}
== History ==
As knows, Bora Lite SoM is suited for compact, cost-sensitive applications. As such, it is often equipped with XC7Z007 or XC7Z014 SoC's, which implement single-core processors. When using a single core
==Testbed==
<pre class="board-terminal">
U-Boot SPL 2017.01-belk-4.1.1 (Jan 08 2020 - 16:46:11)
mmc boot
Trying to boot from MMC1
reading fpga.bit
spl_load_image_fat: error reading image fpga.bit, err - -1
spl: error reading image fpga.bit, err - 1
reading u-boot.img
reading u-boot.img
U-Boot 2017.01-belk-4.1.1 (Jan 08 2020 - 16:46:11 +0100), Build: belk-4.1.1
Model: Bora
Board: Xilinx Zynq
I2C: ready
DRAM: ECC disabled 1 GiB
Relocating to 3ff14000, new gd at 3ead3ee8, sp at 3ead3ec0
NAND: 1024 MiB
MMC: sdhci@e0100000: 0 (SD)
reading bora.env
In: serial@e0001000
Out: serial@e0001000
Err: serial@e0001000
Model: Bora
Board: Xilinx Zynq
SF: Detected is25lp128 with page size 256 Bytes, erase size 64 KiB, total 32 MiB
SOM ConfigID CRC mismatch for 0xff0101ff (was 0xffffffff, expected 0xca9a6d16) at block 2 (offset 96): using default
SF: Detected is25lp128 with page size 256 Bytes, erase size 64 KiB, total 32 MiB
SOM UniqueID not found, using default
SOM ConfigID#: ffffffff
SOM UniqueID#: ffffffff:ffffffff
ds2431_readmem(): error in chip reset
ds2431_readmem(): error in reading buffer
ds2431_readmem(): error in chip reset
ds2431_readmem(): error in reading buffer
CB ConfigID CRC mismatch for 0x00000000 (was 0x00000000, expected 0x2144df1c) at block 3 (offset 96): using default
CB ConfigID#: ffffffff
CB UniqueID#: 00000000:00000000
Net: ZYNQ GEM: e000b000, phyaddr 7, interface rgmii-id
eth0: ethernet@e000b000
Bora>
</pre>
==Setting up the ''Hello, world!'' project==
