Changes

*copy the <code><bora_repo>/boards/board_parts/zynq/BORA</code> and <code><bora_repo>/boards/board_parts/zynq/BORAX</code> directories directory to <code><vivado_2014.4_install_dirvivado_install_dir>/data/boards/board_parts/zynq/</code> :

sudo cp -r boards/board_parts/zynq/BORA /opt/Xilinx/Vivado/2014.4<Vivado_version>/data/boards/board_parts/zynq/sudo cp -r boards/board_parts/zynq/BORAX /opt/Xilinx/Vivado/2014.4/data/boards/board_parts/zynq/

*launch the Vivado Design Suite with the following commands{{efn|In a 32 bit system, Vivado settings are configured with the following command <code>/opt/Xilinx/Vivado/2014.4<Vivado_version>/settings32.sh</code>}}{{efn|Passing the -tclargs "-bitstream" parameters allows for automatic building of the FPGA bitstream.}}:

. /opt/Xilinx/Vivado/2014.4<Vivado_version>/settings64.sh

*at the end of the bitstream build process, the <code>build_project</code> script allows to automatically export hardware and lauch SDK to build the FSBL.*once the Xilinx SDK is ready, perform the following operations from the GUI:**Click on 'For 'File -> New -> Application Project''**select the Project Name: BELK <code>bora_FSBL</code>**Click = 3.0.2''Next'and '**Select ''Template: Zynq FSBL''**Click on ''Finish''**apply the patch, right-clicking on bora_FSBL in Project Explorer and then clicking on Team -> Apply PatchBXELK <= 1.0.*from 1''Browse...'' open : please follow the file <code><bora_repo>[[Creating_and_building_example_Vivado_project_(BELK/patch/belk-sd-boot.patch</code>BXELK)#FSBL_project_build | FSBL build instructions]]**Click For ''Next'BELK-4.0.0'**Select ''Apply the patch to the selected file, folder or projectand '': and select <code>main.c</code> from ''bora_FSBL BXELK-> src''**Click 2.0.0''Next''**Check that the patch there is correctly applied no need to the source code and click on ''Finish''**With the same procedure apply patches build FSBL. Instead PS configurations files are used to fix DDR3 CKE deassertion time (see also: http://wwwbuild U-boot binaries.xilinx.com/support/answers/65145.html):***apply Copy the <code><bora_repo>/patch/AR65145_ps7_init_c.patch</code> on <code>ps7_initps7_init_gpl.c</code> under ''bora_wrapper_hw_platform_0''***apply and <code><bora_repo>/patch/AR65145_ps7_init_tclps7_init_gpl.patchh</code> on <source files into U-boot source code>ps7_init.tcl</code> under ''bora_wrapper_hw_platform_0''*the FSBL (ELF file) is built automatically*create the binary from the FSBL ELF chosing one of directory using the following optionscommand example for Bora:**manually launch the command: <code>arm-xilinx-eabi-objcopy -v -O binary cp $PROJ_DIR/bora.sdksrcs/SDKsources_1/SDK_Exportbd/bora_FSBLbora/Debugip/bora_FSBL.elf $PROJ_DIRbora_processing_system7_0_0/boraps7_init_gpl.sdk* <U-boot_src_dir>/SDKboard/SDK_Exportdave/bora_FSBLbora/Debugbora/bora_FSBL.bin</code>:*this step is board dependent**configure the automatic binary generation on project build. In ''Project Explorer'', rightFollow [[Building_U-click on <code>bora_FSBL<Boot_(BELK/code> project and select ''C/C++ Build Settings'' and add the command <code>arm-xilinx-eabi-objcopy -v -O binary ${ProjName}.elf ${ProjName}.bin</code> on ''PostBXELK) | U-boot build instructions]] to build steps''*create the <code>BOOT.bin</code> image (single file including FSBL, FPGA and U-boot for uSD boot):**select the <code>bora_FSBL</code> project in ''Project Explorer''**click on ''Xilinx Tools -> Create Zynq Boot Image''*if the project is correctly configured, the tool builds automatically all the component listed in the form, so just add U-Boot to the list. *otherwise, select ''Create using new BIF file'' and set the output path and in ''Boot image partitions'' add the following files:**bora_FSBL.elf, which can be found in the project <code>Debug</code> directory. N.B. check PS configurations (please note that the <u>''Partition Type'' for FSBL is ''bootloader''<Default BELK/u>***<code>bora_wrapper.bit</code>, which BXELK PS configuration is the bitstream generated already used by the Vivado project (<u>''Partition Type'' must be ''Datafile''</u>)**<code>udefault in U-boot.elf</code>, which is the compiled U-Boot with <code>.elf</code> extension (<u>''Partition Type'' must be ''Datafile''</u>release)*in ''Output path'', select the path for the <code>BOOT.bin</code> file

*this applies the default settings for BORA/BORAX and creates the I/O ports for the DDR and MIO pins **for '''BELK <= 3.0.2''' and '''BXELK <= 1.0.1''': the default settings automatically creates also connections for the UART_0 and CAN_0 interfaces**for '''BELK-4.0.0''' and '''BXELK-2.0.0''': UART_0 and CAN_0 connections must be manually created by right-clicking on each port (where mouse cursor switch to ''pencil'') and selecting ''Make External'' or with keyboard shortcut <code>Ctrl+T</code>.

**'''Vivado v2014.4 only''': With the same procedure apply patches to fix DDR3 CKE deassertion time (see also: http://www.xilinx.com/support/answers/65145.html):

**this step is board dependent** manually launch the command: <code>arm-xilinx-eabi-objcopy -v -O binary $PROJ_DIR/bora.sdk/SDK/SDK_Export/bora_FSBL/Debug/bora_FSBL.elf $PROJ_DIR/bora.sdk/SDK/SDK_Export/bora_FSBL/Debug/bora_FSBL.bin</code>**this step is board dependent

**for Bora: select the <code>bora_FSBL</code> project in ''Project Explorer''

***<code>bora_wrapper.bit</code>, which is the bitstream generated by the Vivado project (<u>''Partition Type'' must be ''Datafile''</u>)