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==Introduction==
3 versioniReset scheme is strictly related to power supply unit. As such, reading of [[Power_(AXELULite)|this page]] is strongly recommended.
== Reset scheme and control signals ==
The following devices can assert this active-low signal:
* PMIC
* multiple-voltage monitor: this device monitors critical power voltages and triggers a reset pulse in case any of these exhibits a brownout condition .
Since SPI NOR flash can be used as boot device, CPU_PORn is connected to this device too. This guarantees it is in a known state when reset signal is released.
=== Handling CPU-initiated software reset ===
By default, iMX6UL processor does not assert any external signal when it initiates a software reset sequence. This might not guarantee a safe system reset in all conditions. For these reasons, AXELULite integrates a specific circuit that, in combination with the use on iMX6UL watchdog timer (WDT), guarantees a full hardware reset in case a software reset is issued. It is worth remembering that when this reset is triggered, a full power up cycle is issued. This technique makes use of the GPIO1_IO08 pin. Particular attention needs to be paid in case this pin needs to be used at carrier board level as well. For more details please contact the [mailto:support-axel@dave.eu technical support].
=== Handling CPU-initiated software reset ==='''By default, MX6 processor does not assert any external signal when it initiates a software reset sequence. Also default software reset implementation does not guarantee that all processor registers are reset properly'''. For these reasons, it This technique is strongly recommended to use a different approach that, in combination with the use of a processor's watchdog timer supported by [[AXELULite_and_SBC_Lynx_Embedded_Linux_Kit_(WDTXUELK), provides a full hardware reset in case a software reset is issued|AXELULite Embedded LinuxKit]].
This technique is implemented in [[Axel_Embedded_Linux_Kit_(XELK)|XELK]]. At software level, U-Boot and Linux kernel software reset routines make use of processor's WDT #2 to assert the WDOG2_B reset signal. This signal in turn is routed to GPIO_1 pad (MUX mode = 1). At hardware level, this signal is AC-coupled to a 3-state output buffer (please refer to U22 chip of [[AxelEVB-Lite]] carrier board), driving PMIC_PWRON.=References=={{reflist}}
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