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[[File:AXELULite-reset-scheme.png|thumb|center|600px|Simplified block diagram of reset circuitry and voltage monitoring]]
=== PMIC_VSNVS VDD_SNVS_IN ===Some signals that are related to reset circuitry are pulled-up to PMIC_VSNVSVDD_SNVS_IN. This voltage is generated by PMIC PF0100PF3000's VSNVS LDO/Switch and its actual value depends on:* voltage applied to PMICS's PF3000 VIN pin** in case of AxelLite AXELULite this pin is connected to 3.3VIN VIN_SOM power rail* voltage applied to PMICS's PF3000 LICELL pin** in case of AxelLite AXELULite this pin is connected to pin 14 of SODIMM connector (PMIC_LICELL)* PMIC's VSNVSCTL register configuration.
Hence '''it is recommended that system designer takes into account these factors in order to properly manage these signals at carrier board level'''.
For more details please refer to section ''VSNVS LDO/Switch'' of ''MMPF0100 Freescale Semiconductor PF3000 Advance Information'' document<ref name="PF3000">Freescale Semiconductor, PF3000 Advance Information - Power Management Integrated Circuit (PMIC) for i.MX 7 & i.MX 6SL/SX/UL</ref>.
=== CPU_PORn ===
