Bureaucrats, dave_user, Administrators
4,650
edits
Changes
→J2 even pins (2 to 140)
| J2.64||DGND||DGND||-||-||G||-||Digital ground
|-
| J2.66||VDDIO_BANK34||FPGA.VCCO_34||K6<br>H2<br>L3<br>N7<br>P4<br>R1||Bank 34||S||User defined||Bank34 I/O Power Supply
|-
| J2.68||VDDIO_BANK34||FPGA.VCCO_34||K6<br>H2<br>L3<br>N7<br>P4<br>R1||Bank 34||S||User defined||Bank34 I/O Power Supply
|-
| J2.70||VDDIO_BANK34||FPGA.VCCO_34||K6<br>H2<br>L3<br>N7<br>P4<br>R1||Bank 34||S||User defined||Bank34 I/O Power Supply
|-
| J2.72||VDDIO_BANK34||FPGA.VCCO_34||K6<br>H2<br>L3<br>N7<br>P4<br>R1||Bank 34||S||User defined||Bank34 I/O Power Supply
|-
| J2.74||RFU||-||-||-||-||-||Reserved for future use. Must be left floating.
| J2.102||DGND||DGND||-||-||G||-||Digital ground
|-
| J2.104||PS_MIO50_501||CPU.PS_MIO50_501<br>USBOTG.RESETB||D10<br>22||BANK 501||I/O||1.8V||For further details, please refer to [[Reset_scheme_(BoraXpress)#PS_MIO50_501_.28J2.104.29 | Reset_scheme_(BoraXpress)#PS_MIO50_501]]
|-
| J2.106||PS_MIO51_501||CPU.PS_MIO51_501<br>ETHPHY1GB.RESET_N||C13<br>42||BANK 501||I/O||1.8V||For further details, please refer to [[Reset_scheme_(BoraXpress)#PS_MIO51_501_.28J2.106.29 | Reset_scheme_(BoraXpress)#PS_MIO51_501 ]]
|-
| J2.108||SOM_PGOOD||SOM_PGOOD_LOGIC.OUT||n.a.||3.3V||O||3.3V||Internally connected to DGND via 100K resistor
|-
| J2.110||CB_PWR_GOOD||1.0VREGULATOR.ENABLE<br>SOM_PGOOD_LOGIC.IN||n.a.||3.3VIN||I||3.3V||Internally connected to 3.3VIN via 10K resistor
|-
| J2.112||SYS_RSTn||CPU.PS_SRST_B_501 ||C14||BANK 501||I||1.8V||Internally connected to 1.8V via 20K resistor
|-
| J2.114||PORSTn||CPU.PS_POR_B_500<br>SV1.~RST<br>SV2.~RST<br>WD.~WDO<br>NOR.~RESET/RFU||B18<br>5<br>5<br>7<br>A4||BANK 500||I/O||3.3V||Internally connected to 3.3VIN via 2.2K resistor.<br>For further details, please refer to [[Reset_scheme_(BoraXpress)#PORSTn_.28J2.114.29 | Reset_scheme_(BoraXpress)#PORSTn ]]
|-
| J2.116||MRSTn||SV1.~MR||6||3.3VIN||I||3.3V||Internally connected to 3.3VIN via 2.2K resistor
