Bureaucrats, dave_user, Administrators
4,650
edits
Changes
→J1 odd pins (1 to 139)
| J1.105||ETH_TXRX0_P||LAN.ETH_TXRX0_P||2||||D||||
|-
| J1.107||DVDDH||LAN.DVDDH||16<br>34<br>40||||||||
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| J1.109||RFU||-||-||-||-||-||Reserved fo future use. Must be left floating.
| J1.119||SPI0_DQ3/MODE0/NAND_IO0||CPU.PS_MIO5_500<br>NOR flash<br>NAND flash||CPU.A20||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
|-
| J1.121||SPI0_DQ2/MODE2/NAND_IO2||CPU.PS_MIO4_500<br>NOR flash<br>NAND flash||CPU.E19||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
|-
| J1.123||SPI0_DQ1/MODE1/NAND_WE||CPU.PS_MIO3_500<br>NOR flash<br>NAND flash||CPU.F17||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
|-
| J1.125||SPI0_DQ0/MODE3/NAND_ALE||CPU.PS_MIO2_500<br>NOR flash<br>NAND flash||CPU.A21||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
|-
| J1.127||DGND||DGND||-||-||-||-||
|-
| J1.129||SPI0_SCLK/MODE4/NAND_IO1||CPU.PS_MIO6_500<br>NOR flash<br>NAND flash||CPU.A19||Bank 500||I/O||3.3V||This signal is pulled up or down by 20kOhm resistor to select proper bootstrap configuration.
|-
| J1.131||NAND_BUSY||CPU.PS_MIO14_500<br>NOR flash<br>NAND flash||CPU.B17||Bank 500||I/O||3.3V||10kOhm pull-up
|-
| J1.133||PS_MIO15_500||"CPU.PS_MIO15_500<br>WDT.WDI
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| "||CPU.E17<br>WDT.1||Bank 500||I/O||3.3V||See also this page
|-
| J1.135||RFU||-||-||-||-||-||Reserved fo future use. Must be left floating.
|-
| J1.137||MEM_WPn||NAND.WP<br>NOR.WP/IO2||NAND.19<br>NOR.C4||||||3.3V||
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| J1.139||DGND||DGND||-||-||-||-||
