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Watchdog (Bora)

987 bytes added, 08:31, 9 October 2015
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{{Applies To Bora}}
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==Description and default configuration==
An external watchdog timer (Maxim MAX6373<ref name="MAX6373">https://www.maximintegrated.com/en/products/power/supervisors-voltage-monitors-sequencers/MAX6373.html</ref>) is connected to the PORSTn signal. During normal operation, the microprocessor should repeatedly toggle the watchdog input WDI before the selected watchdog timeout period elapses to demonstrate that the system is processing code properly. If the μP does not provide a valid watchdog input transition before the timeout period expires, the supervisor asserts a watchdog (WDO) output to signal that the system is not executing the desired instructions within the expected time frame. The watchdog output pulse is used to reset the μP.
Default mounting option is depicted in the following figure.
[[File:Bora-reset-scheme.png|thumb|center|700px|Watchdog timer default mounting option]]
WDI is connected to Zynq's PS_MIO15_500 I/O. This signal is available on Bora connectors as PS_MIO15_500 (J1.133).
[[FileThe MAX6373 watchdog timer (WDT) is pin-selectable. It can be configured through the WD_SET0 (J2.100), WD_SET1 (J2.98) and WD_SET2 (J2.96) signals. As a default, they are configured as follows:Bora*WD_SET2 = 1*WD_SET1 = 0*WD_SET0 = 0This set selects the option*tDELAY = first edge*tWD = 10s.In other words, WDT is started when the first transition on WDI input is detected. Once started, its timeout period is 10s. The first transition of WDI input should be under software control. However, despite of the presence of 22kOhm pull-resetdown on EX_WDT_REARM signal, during power-on sequence a spurious 0-to-1 transition may be observed on EX_WDT_REARM line. The voltage swing of this transition is variable, since it depends on the internal Zynq's pull-up value. In general, <u>WDT may be inadvertently started at power-up</u>, before software takes control of PS_MIO15_500 GPIO. <u>To avoid this situation, it is recommended to add a 2.2kOhm pull-schemedown on carrier board, connected to the PS_MIO15_500 signal</u>.png | 700px]]
An external watchdog (Maxim MAX6373) is connected to the PORSTn signal. During normal operationIn any case, when the microprocessor should repeatedly toggle the watchdog input WDI before the selected watchdog timeout period elapses to demonstrate that the system is processing code properly. If the μP does not provide a valid watchdog input transition before the timeout period expiresstarted, the supervisor asserts a watchdog software (WDObootloader/operating system) output to signal that must take care of toggling the system is not executing the desired instructions within the expected time frame. The watchdog output pulse is used to reset trigger pin (WDI) before the μP. By default WDI is connected to Zynq's PS_MIO15_500 I/O. WDI is available on Bora connectors as EX_WDT_REARMtimeout expiration.
On request==Selecting different configurations==Since WD_SETx signals are routed externally, PS_MIO15_500 WDT configuration can be disconnected from WDI (please contact Sales Department changed by optional circuitry implemented on the carrier board. Different solutions for more details). This configuration provides two independent signals (EX_WDT_REAM and PS_MIO15_500) that allow the implementation of customized solutions watchdog management can be implemented on the carrier board, depending on system requirements. For example you may want The easiest circuit consists of additional pull-up/down resistors connected to use the Zynq's System Watchdog Timer (SWDT) instead WD_SETx pins in order to overrule default configuration. The exhaustive configurations options are listed in table 1 of reference <ref name="MAX6373 to reset the system through PS_MIO15_500 that can be configured as SWDT reset"></ref>.
The MAX6373 watchdog timer is pin-selectable and the timer can be configured through the WD_SET0 (J2.100), WD_SET1 (J2.98) and WD_SET2 (J2.96) signals. As a default, the watchdog is configured on the BORA SOM to trigger at startup. Startup delay ends when WDI sees its first level transition. The default watchdog timeout period is 10 s.
The configuration can be changed by optional external circuitry implemented on the carrier board. There are two available solutions for the watchdog management to be implemented on the carrier board, depending on system requirements:
* adding the WD_SET[2..0] pull-up/pull-down resistors to be able to fully configure the device (in particular, the WD_SET[2..0] = 110 configuration keeps the watchdog timer disabled at startup)
* adding a strong (2K2 Ohm) pull-down on the WDI/EX_WDT_REARM pin, to simply keep the watchdog inactive at startup
When the watchdog is enabledOn request, the software PS_MIO15_500 can be disconnected from WDI (please contact Sales Department for more details). This configuration provides two independent signals (bootloader/operating systemEX_WDT_REARM and PS_MIO15_500) must take care that allow the implementation of toggling customized solutions on carrier board. For example you may want to use the watchdog trigger pin Zynq's System Watchdog Timer (WDISWDT) before instead of MAX6373 to reset the timeout expirationsystem through PS_MIO15_500 that can be configured as SWDT reset. 
Please note that on the BORAEVB carrier board, the watchdog is externally configured as disabled.
 
==References==
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