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→CPU_PORn
Three different sources can assert this active-low signal:
* PMIC
* multiple-voltage monitor: this device monitors several critical power voltages and triggers a reset pulse in case any of these exhibits a brownout condition ** MRSTn: this signal is connected to the RESET IN input of the voltage monitor. MRSTn is pulled-up to processor's I/O voltage with 2.2 kOhm resistor.
* watchdog timer: even if MX6 processor integrates a watchdog timer (WDT), an external WDT (Maxim MAX6373KA+) is avalible to maximize reliability
Since SPI NOR flash can be used as boot device, CPU_PORn is connected to this device too. This guarantees it is in a known state after reset occurrence.
=== Handling CPU initiated reset ===
'''By default, MX6 processor does not assert any external signal when it initiates a reset sequence'''. This behaviour can be changed by acting on WDOG_RESET_B_DEB signal configuration. This signal is driven by MX6's watchdog timer (WDT).
