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Created page with "{{InfoBoxTop}} {{Applies To Bora}} {{InfoBoxBottom}} = Design Overview = The heart of Bora module is composed of the following components: * Xilinx Zynq Z-7010 (XC7Z010) / Z..."
{{InfoBoxTop}}
{{Applies To Bora}}
{{InfoBoxBottom}}
= Design Overview =
The heart of Bora module is composed of the following components:
* Xilinx Zynq Z-7010 (XC7Z010) / Z-7020 (XC7Z020) SoC
* Power supply unit
* DDR memory banks
* NOR and NAND flash banks
* 3x 140 pin connectors with interfaces signals
This chapter shortly describes the main Bora components.
== Processor Info ==
The Zynq™-7000 family is based on the Xilinx Extensible Processing Platform (EPP) architecture. These products integrate a feature-rich dual-core ARM® Cortex™-A9 based processing system (PS) and 28 nm Xilinx programmable logic (PL) in a single device. The ARM Cortex-A9 CPUs are the heart of the PS and also include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces.
The Zynq-7000 family offers the flexibility and scalability of an FPGA, while providing performance, power, and ease of use typically associated with ASIC and ASSPs. The range of devices in the Zynq-7000 AP SoC family enables designers to target cost-sensitive as well as high-performance applications from a single platform using industry-standard tools. While each device in the Zynq-7000 family contains the same PS, the PL and I/O resources vary between the devices. As a result, the Zynq-7000 AP SoC devices are able to serve a wide range of applications including:
* Automotive driver assistance, driver information, and infotainment
* Broadcast camera
* Industrial motor control, industrial networking, and machine vision
* IP and Smart camera
* LTE radio and baseband
* Medical diagnostics and imaging
* Multifunction printers
* Video and night vision equipment
The following table shows a comparison between the devices, highlighting the differences:
{| class="wikitable" |
| align="center" style="background:#f0f0f0;"|'''Processor'''
| align="center" style="background:#f0f0f0;"|'''Programmable logic cells'''
| align="center" style="background:#f0f0f0;"|'''LUTs'''
| align="center" style="background:#f0f0f0;"|'''Flip flops'''
| align="center" style="background:#f0f0f0;"|'''Extensible block RAM'''
| align="center" style="background:#f0f0f0;"|'''DSP slices'''
| align="center" style="background:#f0f0f0;"|'''Peak DSP performance'''
|-
| XC7Z010 ||28K Logic Cells ||17600 ||35200 ||240 KB ||80 ||58 GMACs
|-
| XC7Z020 ||85K Logic Cells ||53200 ||106400 ||560 KB ||220 ||158 GMACs
|-
|+ align="bottom" style="caption-side: bottom" | Table: XC7-Z0x0 comparison
|}
== RAM memory bank ==
DDR3 SDRAM memory bank is composed by 2x 16-bit width chips resulting in a 32-bit combined width bank. The following table reports the SDRAM specifications:
{| class="wikitable" |
|-
| '''CPU connection'''||SDRAM bus
|-
| '''Size min'''||512 MB
|-
| '''Size max'''||1 GB
|-
| '''Width'''||32 bit
|-
| '''Speed'''||533 MHz
|-
|}
== NOR flash bank ==
NOR flash is a Serial Peripheral Interface (SPI) device. By default this device is connected to SPI channel 0 and acts as boot memory. The following table reports the NOR flash specifications:
{| class="wikitable" |
|-
| '''CPU connection'''||SPI Channel 0
|-
| '''Size min'''||8 MB
|-
| '''Size max'''||64 MB
|-
| '''Chip select'''||SPI_CS0n
|-
| '''Bootable'''||Yes
|-
|}
== NAND flash bank ==
On board main storage memory is a 8-bit wide NAND flash. By default it is connected to chip select. The following table reports the NAND flash specifications:
{| class="wikitable" |
|-
| '''CPU connection'''||Static memory controller
|-
| '''Page size'''|| 512 byte, 2 kbyte or 4 kbyte
|-
| '''Size min'''||128 MB
|-
| '''Size max'''||2 GB
|-
| '''Width'''||8 bit
|-
| '''Chip select'''||NAND_CS0
|-
| '''Bootable'''||Yes
|-
|}
== Memory map ==
This section will be completed in a future version of this manual.
== Power supply unit ==
Bora, as the other Ultra Line CPU modules, embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters. For detailed information, please refer to Section 5.1.
== CPU module connectors ==
All interface signals Bora provides are routed through three 140 pin 0.6mm pitch stacking connectors (named J1, J2 and J3). The dedicated carrier board must mount the mating connectors and connect the desired peripheral interfaces according to Bora pinout specifications.
{{Applies To Bora}}
{{InfoBoxBottom}}
= Design Overview =
The heart of Bora module is composed of the following components:
* Xilinx Zynq Z-7010 (XC7Z010) / Z-7020 (XC7Z020) SoC
* Power supply unit
* DDR memory banks
* NOR and NAND flash banks
* 3x 140 pin connectors with interfaces signals
This chapter shortly describes the main Bora components.
== Processor Info ==
The Zynq™-7000 family is based on the Xilinx Extensible Processing Platform (EPP) architecture. These products integrate a feature-rich dual-core ARM® Cortex™-A9 based processing system (PS) and 28 nm Xilinx programmable logic (PL) in a single device. The ARM Cortex-A9 CPUs are the heart of the PS and also include on-chip memory, external memory interfaces, and a rich set of peripheral connectivity interfaces.
The Zynq-7000 family offers the flexibility and scalability of an FPGA, while providing performance, power, and ease of use typically associated with ASIC and ASSPs. The range of devices in the Zynq-7000 AP SoC family enables designers to target cost-sensitive as well as high-performance applications from a single platform using industry-standard tools. While each device in the Zynq-7000 family contains the same PS, the PL and I/O resources vary between the devices. As a result, the Zynq-7000 AP SoC devices are able to serve a wide range of applications including:
* Automotive driver assistance, driver information, and infotainment
* Broadcast camera
* Industrial motor control, industrial networking, and machine vision
* IP and Smart camera
* LTE radio and baseband
* Medical diagnostics and imaging
* Multifunction printers
* Video and night vision equipment
The following table shows a comparison between the devices, highlighting the differences:
{| class="wikitable" |
| align="center" style="background:#f0f0f0;"|'''Processor'''
| align="center" style="background:#f0f0f0;"|'''Programmable logic cells'''
| align="center" style="background:#f0f0f0;"|'''LUTs'''
| align="center" style="background:#f0f0f0;"|'''Flip flops'''
| align="center" style="background:#f0f0f0;"|'''Extensible block RAM'''
| align="center" style="background:#f0f0f0;"|'''DSP slices'''
| align="center" style="background:#f0f0f0;"|'''Peak DSP performance'''
|-
| XC7Z010 ||28K Logic Cells ||17600 ||35200 ||240 KB ||80 ||58 GMACs
|-
| XC7Z020 ||85K Logic Cells ||53200 ||106400 ||560 KB ||220 ||158 GMACs
|-
|+ align="bottom" style="caption-side: bottom" | Table: XC7-Z0x0 comparison
|}
== RAM memory bank ==
DDR3 SDRAM memory bank is composed by 2x 16-bit width chips resulting in a 32-bit combined width bank. The following table reports the SDRAM specifications:
{| class="wikitable" |
|-
| '''CPU connection'''||SDRAM bus
|-
| '''Size min'''||512 MB
|-
| '''Size max'''||1 GB
|-
| '''Width'''||32 bit
|-
| '''Speed'''||533 MHz
|-
|}
== NOR flash bank ==
NOR flash is a Serial Peripheral Interface (SPI) device. By default this device is connected to SPI channel 0 and acts as boot memory. The following table reports the NOR flash specifications:
{| class="wikitable" |
|-
| '''CPU connection'''||SPI Channel 0
|-
| '''Size min'''||8 MB
|-
| '''Size max'''||64 MB
|-
| '''Chip select'''||SPI_CS0n
|-
| '''Bootable'''||Yes
|-
|}
== NAND flash bank ==
On board main storage memory is a 8-bit wide NAND flash. By default it is connected to chip select. The following table reports the NAND flash specifications:
{| class="wikitable" |
|-
| '''CPU connection'''||Static memory controller
|-
| '''Page size'''|| 512 byte, 2 kbyte or 4 kbyte
|-
| '''Size min'''||128 MB
|-
| '''Size max'''||2 GB
|-
| '''Width'''||8 bit
|-
| '''Chip select'''||NAND_CS0
|-
| '''Bootable'''||Yes
|-
|}
== Memory map ==
This section will be completed in a future version of this manual.
== Power supply unit ==
Bora, as the other Ultra Line CPU modules, embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters. For detailed information, please refer to Section 5.1.
== CPU module connectors ==
All interface signals Bora provides are routed through three 140 pin 0.6mm pitch stacking connectors (named J1, J2 and J3). The dedicated carrier board must mount the mating connectors and connect the desired peripheral interfaces according to Bora pinout specifications.
