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→Feature Summary
| Cache||L1: 32Kbyte instruction, 32Kbyte data<br>L2: 512Kbyte for each core ||
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| RAM|| DDR3 SDRAM @ 533 MHz<br>Up to 1 GB||
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| Storage||Flash NOR SPI (8, 16, 32 MB)<br>Flash NAND (all sizes, on request)||
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|+ align="bottom" style="caption-side: bottom" | Table: CPU and Memories
| Coprocessors|| NEON™ & Single / Double Precision<br>Floating Point for each processor||
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| USB||Up to 2x 2.0 OTG ports||
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| UARTs||Up to 2x UART ports||
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| GPIO||Up to x lines, shared with other functions (interrupts available)||
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| Networks||Fast Ethernet 10/100Mbps||
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| CAN||2x full CAN 2.0B compliant interfaces||
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| SD/MMC||2x SD/SDIO 2.0/MMC3.31 compliant controllers||
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| Serial buses||2x full-duplex SPI ports with three peripheral chip selects<br>2x master and slave I²C interfaces||
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| Timers||2x triple timers/counters (TTC)||
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| RTC ||On board (DS3232), external battery powered||
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| Debug||JTAG IEEE 1149.1 Test Access Port<br>CoreSight™ and Program Trace Macrocell (PTM)||
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|+ align="bottom" style="caption-side: bottom" | Table: Peripherals
