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<section end=SPI/>
=== Static memory controller ===
<section begin=NAND/>
Static memory controller (SMC) signals are routed to the connectors to connect an external flash NAND memory chip. The following table describes the interface signals:
{| class="wikitable"
|-
!Pin name
!Conn. pin
!Function
!Notes
|-
|NAND_CS0 || J1.122 || NAND flash chip select || MIO bank 0, pin 0
|-
|NAND_IO0 || J1.119 || NAND I/O 0 || MIO bank 0, pin 5
|-
|NAND_IO1 || J1.129 || NAND I/O 1 || MIO bank 0, pin 6
|-
|NAND_IO2 || J1.121 || NAND I/O 2 || MIO bank 0, pin 4
|-
|NAND_IO3 || J1.124 || NAND I/O 3 || MIO bank 0, pin 13
|-
|NAND_IO4 || J1.126 || NAND I/O 4 || MIO bank 0, pin 9
|-
|NAND_IO5 || J1.128 || NAND I/O 5 || MIO bank 0, pin 10
|-
|NAND_IO6 || J1.132 || NAND I/O 6 || MIO bank 0, pin 11
|-
|NAND_IO7 || J1.134 || NAND I/O 7 || MIO bank 0, pin 12
|-
|NAND_WE || J1.123 || NAND write enable || MIO bank 0, pin 3
|-
|NAND_ALE || J1.125 || NAND address latch || MIO bank 0, pin 2
|-
|NAND_RB || J1.136 || NAND ready/busy || MIO bank 0, pin 8
|-
|NAND_CLE || J1.138 || NAND command latch enable || MIO bank 0, pin 7
|-
|}
<section end=NAND/>
=== I²C0 ===
<section begin=I2C0/>
