Processing system peripherals (BoraLite)
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Contents
Introduction[edit | edit source]
Bora modules implement a number of peripheral interfaces through the J1 connector. The following notes apply to those interfaces:
- Some interfaces/signals are available only with/without certain configuration options of the BORA Lite module.
- The peripherals described in the following sections represent the default configuration for the BORA Lite SOM, which match with the features provided by the electronics implemented on the module. As an example, the Zynq device provides two USB 2.0 controllers, but the Bora SOM provides one USB OTG port, with transceiver connected to one of the controllers and signals routed to the module connectors. Therefore, only one USB port will be described in details.
Notes on pin assignment[edit | edit source]
For detailed information on MIO and EMIO configuration, please refer to section 2.5.1 /“I/O Peripheral (IOP) Interface Routing”) of the Zynq-7000 Technical Reference Manual. On the Bora SOM, the MIO module is configured for providing a standard set of peripherals (eg, Ethernet, USB, …); some pins of the EMIO are also used to implement some functions (eg: I2C, specific I/Os). Plese refer to the following sections for detailed information.
PS interfaces[edit | edit source]
The 54 pins of the MIO module are assigned as reported in the following table:
| MIO Pins | Function |
|---|---|
| MIO[0:14] | Quad-SPI and NAND flash |
| MIO[15] | EX_WDT_REARM (watchdog WDI) Optionally, it can act as SWDT reset out |
| MIO[16:27] | Gigabit Ethernet |
| MIO[28:39] | USB On-The-Go |
| MIO[40:45] | SD/SDIO/MMC |
| MIO[46:47] | I²C0 |
| MIO[48:49] | UART1 |
| MIO[50] | USB0 PHY reset |
| MIO[51] | Ethernet PHY reset |
| MIO[52] | Ethernet Management Data Clock input |
| MIO[53] | Ethernet Management Data Input/Output |
Gigabit Ethernet[edit | edit source]
On-board Ethernet PHY (Micrel KSZ9031RNX) provides interface signals required to implement the 10/100/1000 Mbps Ethernet port. The transceiver is connected to the Gigabit Ethernet Controller (GEM) through RGMII interface on MIO bank 1, pins PS_MIO[16:27]. For further details (eg: connection and selection of the magnetics), please refer to the Micrel KSZ9031RNX datasheet. The following table describes the interface signals:
| Pin name | Conn. pin | Function | Notes |
|---|---|---|---|
| ETH_TXRX0_P | J1.19 | Media Dependent Interface[0], positive pin | - |
| ETH_TXRX0_M | J1.21 | Media Dependent Interface[0], negative pin | - |
| ETH_TXRX1_P | J1.23 | Media Dependent Interface[1], positive pin | - |
| ETH_TXRX1_M | J1.25 | Media Dependent Interface[1], negative pin | - |
| ETH_TXRX2_P | J1.27 | Media Dependent Interface[2], positive pin | - |
| ETH_TXRX2_M | J1.29 | Media Dependent Interface[2], negative pin | - |
| ETH_TXRX3_P | J1.31 | Media Dependent Interface[3], positive pin | - |
| ETH_TXRX3_M | J1.33 | Media Dependent Interface[3], negative pin | - |
| ETH_LED1 | J1.13 | Activity LED | - |
| ETH_LED2 | J1.15 | Link LED | - |
USB[edit | edit source]
BORA Lite provides one USB 2.0 (Full Speed, up to 480 Mbps) port with on-board PHY (SMSC USB3317) and support to the On-The-Go (OTG) specifications. The transceiver is connected to the USB1 controller (MIO bank 1, pins PS_MIO[28:39]). The following table describes the interface signals:
| Pin name | Conn. pin | Function | Notes |
|---|---|---|---|
| USBP1 | J1.200 | D+ pin of the USB cable | - |
| USBM1 | J1.202 | D- pin of the USB cable | - |
| USBOTG_CPEN | J1.194 | External 5 volt supply enable | This pin is used to enable the external Vbus power supply |
| OTG_VBUS | J1.196 | VBUS pin of the USB cable | - |
| OTG_ID | J1.198 | ID pin of the USB cable | For non-OTG applications this pin can be floated. For an A-device ID is grounded. For a B-device ID is floated. |
Quad-SPI[edit | edit source]
Quad-SPI is used to access multi-bit serial flash memory devices for high throughput and low pin count applications. The controller operates in one of three modes: I/O mode, linear addressing mode, and legacy SPI mode. The following table describes the interface signals:
| Pin name | Conn. pin | Function | Notes |
|---|---|---|---|
| SPI0_CS0 | J1.44 | Chip select 0 | MIO bank 0, pin 1 |
| SPI0_DQ0 | J1.46 | 1-bit: Master Output 2-bit: I/O0 4-bit: I/O0 |
MIO bank 0, pin 2 |
| SPI0_DQ1 | J1.48 | 1-bit: Master Input 2-bit: I/O1 4-bit: I/O1 |
MIO bank 0, pin 3 |
| SPI0_DQ2 | J1.50 | 1-bit: Write protect 2-bit: Write protect 4-bit: I/O0 |
MIO bank 0, pin 4 |
| SPI0_DQ3 | J1.52 | 1-bit: Hold 2-bit: Hold 4-bit: I/O3 |
MIO bank 0, pin 5 |
| SPI0_SCLK | J1.54 | Serial clock | MIO bank 0, pin 6 |
Static memory controller[edit | edit source]
Static memory controller (SMC) signals are routed to the connectors to connect an external flash NAND memory chip. The following table describes the interface signals:
| Pin name | Conn. pin | Function | Notes |
|---|---|---|---|
| NAND_CS0 | J1.122 | NAND flash chip select | MIO bank 0, pin 0 |
| NAND_IO0 | J1.119 | NAND I/O 0 | MIO bank 0, pin 5 |
| NAND_IO1 | J1.129 | NAND I/O 1 | MIO bank 0, pin 6 |
| NAND_IO2 | J1.121 | NAND I/O 2 | MIO bank 0, pin 4 |
| NAND_IO3 | J1.124 | NAND I/O 3 | MIO bank 0, pin 13 |
| NAND_IO4 | J1.126 | NAND I/O 4 | MIO bank 0, pin 9 |
| NAND_IO5 | J1.128 | NAND I/O 5 | MIO bank 0, pin 10 |
| NAND_IO6 | J1.132 | NAND I/O 6 | MIO bank 0, pin 11 |
| NAND_IO7 | J1.134 | NAND I/O 7 | MIO bank 0, pin 12 |
| NAND_WE | J1.123 | NAND write enable | MIO bank 0, pin 3 |
| NAND_ALE | J1.125 | NAND address latch | MIO bank 0, pin 2 |
| NAND_RB | J1.136 | NAND ready/busy | MIO bank 0, pin 8 |
| NAND_CLE | J1.138 | NAND command latch enable | MIO bank 0, pin 7 |
I²C0[edit | edit source]
This I²C module is a bus controller that can function as a master or a slave in a multi-master design. It supports an extremely wide clock frequency range up to 400 Kb/s. I²C0 is internally connected to the following devices:
The following table describes the interface signals:
| Pin name | Conn. pin | Function | Notes |
|---|---|---|---|
| PS_MIO46_501 | J1.32 | I2C clock | - |
| PS_MIO47_501 | J1.28 | I2C data | - |
SD/SDIO[edit | edit source]
The SD/SDIO controller controller is compatible with the standard SD Host Controller Specification Version 2.0 Part A2. The core also supports up to seven functions in SD1, SD4, but does not support SPI mode. It does support SD high-speed (SDHS) and SD High Capacity (SDHC) card standards. The SD/SDIO controller also supports MMC3.31.
The following table describes the interface signals:
| Pin name | Conn. pin | Function | Notes |
|---|---|---|---|
| PS_SD0_CLOCK | J1.37 | SD/SDIO/MMC clock | - |
| PS_SD0_CMD | J1.39 | SD/SDIO/MMC command | - |
| PS_SD0_DAT0 | J1.40 | SD/SDIO/MMC data 0 | - |
| PS_SD0_DAT1 | J1.38 | SD/SDIO/MMC data 1 | - |
| PS_SD0_DAT2 | J1.36 | SD/SDIO/MMC data 2 | - |
| PS_SD0_DAT3 | J1.34 | SD/SDIO/MMC data 3 | - |
UART1[edit | edit source]
The UART controller is a full-duplex asynchronous receiver and transmitter that supports a wide range of programmable baud rates and I/O signal formats. UART1 port is routed to the SOM connectors as a 2-wire interface. The following table describes the interface signals:
| Pin name | Conn. pin | Function | Notes |
|---|---|---|---|
| PS_UART1_RX | J1.24 | UART Receive line | - |
| PS_UART1_TX | J1.26 | UART Transmit line | - |
JTAG[edit | edit source]
The Zynq-7000 family of AP SoC devices provides debug access via a standard JTAG (IEEE 1149.1) debug interface. This JTAG port grants access to the device chain composed of both the CPU core and the FPGA part. The following table describes the interface signals:
| Pin name | Conn. pin | Function | Notes |
|---|---|---|---|
| JTAG_TCK | J2.2 | JTAG TCK | - |
| JTAG_TMS | J2.3 | JTAG TMS | - |
| JTAG_TDO | J2.4 | JTAG TDO | - |
| JTAG_TDI | J2.5 | JTAG TDI | - |
More information about the JTAG connector at the this page
