Open main menu

DAVE Developer's Wiki β

Changes

Reset scheme (Naon)

597 bytes added, 14:06, 2 May 2012
no edit summary
{{AppliesToNaon}}
{{InfoBoxBottom}}
==Accessible reset signals==
Five different signals are provided by Naon SOM. FOllowing sections describes in more detail each one.
===MRST (J2.102)===
===PORSTn (J2.109)===
PORSTn is a bidirectional open-drain signal. It is connected to:
*PORn input (Power-on Reset) of DM8148 processor* output of voltage monitor ([#Voltage monitor])* NRESPWRON2 output of PMIC.Internal pullup is 10kOhm.
===RSTOUTn (J2.91)===
This signal is asserted by DM8148 processor until it gets out of reset. It is usually used to reset external memories and peripherals conneteced to processor. It is connected to:
* RSTOUT_WD_OUTn pad of DM8148 processor
* peripherals and memories.
In case it is used to reset devices on carrier board, its driving capability has to be taken into account.
===CPU_RESETn (J2.15)===
External Warm Reset
===JTAG_TRSTn (J2.100)===
Emulation Warm Reset
==Voltage monitor==