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The LVDS interface available on the Evaluation Kit at the connector ''TBD:Jxxx''J20. J20 is a Hirose (cod. DF13A-20DP-1.25V) double row 1.25mm pitch miniature crimping connector

''Jxx'' is The [[AXEL ULite SOM/AXEL ULite Evaluation Kit | AXEL ULite Evaluation Kit]] provides a ''TBD:connector18-type'' header connector for the RS232 two-wires UART3 port, used for debug purposes (bootloader and operating system serial console)bit LVDS interface.

[[File:{{{nome-som}}AXEL_ULite-EVB-LVDS-connector.png|thumb|center|500px|LVDS connector]]

The LVDS is generated, starting from the RGB i.MX6UL SOC, with a RGB-to-LVDS [https://www.ti.com/lit/ds/symlink/ds90c385a.pdf DS90C385A] LVDS transmitter. For the RGB pin mapping, please refer to the [[AXEL_ULite_SOM/AXEL_ULite_Hardware/Peripherals/RGB | AXEL_ULite ]] RGB interface description.  The following table tables describes the interface signals:

|1,2,4,6,,7,8,10| -| N3.A.3V_LCD || N.C3.| Not connected3 V LCD PSU

| 3, 4, 7, 10, | J1.18913, 16, 19 | RS232_RX- | Receive line| Ground

| 35 | J1.187| RS232_TXLVDS_TX0_N | Transmit line| LVDS Data 0 -

| 6 || LVDS_TX0_P || LVDS Data 0 +|-| 8 || LVDS_TX1_N || LVDS Data 1 -|-| 9|| LVDS_TX1_P || LVDS Data 1 +|-| 11 || LVDS_TX2_N || LVDS Data 2 -|-| 12 || LVDS_TX2_P || LVDS Data 2 +|-| 14 || LVDS_CLK_N || LVDS Clock -|-| 15 || LVDS_CLK_P || LVDS Clock +|-| 17 || PWM || backlight PWM control |-| 18 || 5V || backlight 5V PSU | -| DGND19 || GPIO || 3V3 or GND (mount option, default = GND) | Ground-| 20 || BL_EN || backlight enable

UART3 * LVDS is mapped to <code>/dev/ttymxc2fb0</code> device in Linux. The peripheral is used as the default serial console, both for the bootloader and the kernel. === Device usage === To connect to the debug serial port: # connect the DB9 adapter bracket to the J22 connector on the SBCX board# connect a serial cable between DB9 connector and PC COM port through a NULL-modem cable (not provided)# start your favorite terminal emulator software on PC (eg: PuTTY); communication parameters are: 115200,N,8,1