Bureaucrats, dave_user, Administrators
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→Handling CPU-initiated software reset
For these reasons, it is strongly recommended to use a different approach that, in combination with the use of a processor's watchdog timer (WDT), provides a full hardware reset in case a software reset is issued.
This technique is implemented in [[DESK-MX6-L]]. At software level, U-Boot and Linux kernel software reset routines make use of processor's WDT #2 to assert the WDOG2_B reset signal. This signal in turn is routed to GPIO_1 pad (MUX mode = 1). At hardware level, this signal is AC-coupled to a 3-state output buffer (please refer to U22 chip of [[http://mirror.dave.eu/axel/hw/AxelEVB/rev-A/axelevb-lite_S-EVBA1000C1R_1.0.8.pdf AxelEVB-Lite]] carrier board), driving PMIC_PWRON.
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[[Category:AXEL Lite]]
