a000298_approval, dave_user
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edits
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Created page with "<section begin="History" /> {| style="border-collapse:collapse; " ! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History |- ! style="bo..."
<section begin="History" />
{| style="border-collapse:collapse; "
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Feb 2021
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
|-
|-
|}
<section end="History" />
<section begin="Body" />
==Peripheral NPU ==
The Neural Processign Unit (NPU) available on ORCA is based on iMX8MPlus SoC.
=== Description ===
The Neural Processing Unit (NPU) core accelerates vision image processing functions and provides enhanced performance for real-time use cases with hardware support for the OpenVX API.
Key features of the NPU block include:
* OpenVX 1.2 compliance, including extensions
* Convolutional Neural Network acceleration
* IEEE 32-bit floating-point pipeline in PPU shaders.
* Ultra-threaded parallel processing unit
* Low bandwidth at both high and low data rates
* Low CPU loading
* MMU functionality supported
* Performance Counters for DMA Profiling
* Data transfers between Neural Network Engines and the Parallel Processing Unit, with SRAM as local storage
* Neural Network Engine and Parallel Processing Unit synchronization with hardware semaphore
----
[[Category:ORCA]]
{| style="border-collapse:collapse; "
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Feb 2021
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
|-
|-
|}
<section end="History" />
<section begin="Body" />
==Peripheral NPU ==
The Neural Processign Unit (NPU) available on ORCA is based on iMX8MPlus SoC.
=== Description ===
The Neural Processing Unit (NPU) core accelerates vision image processing functions and provides enhanced performance for real-time use cases with hardware support for the OpenVX API.
Key features of the NPU block include:
* OpenVX 1.2 compliance, including extensions
* Convolutional Neural Network acceleration
* IEEE 32-bit floating-point pipeline in PPU shaders.
* Ultra-threaded parallel processing unit
* Low bandwidth at both high and low data rates
* Low CPU loading
* MMU functionality supported
* Performance Counters for DMA Profiling
* Data transfers between Neural Network Engines and the Parallel Processing Unit, with SRAM as local storage
* Neural Network Engine and Parallel Processing Unit synchronization with hardware semaphore
----
[[Category:ORCA]]
